From: Maciej W. Rozycki <macro@embecosm.com>
Date: Fri, 28 Jan 2022 11:55:12 +0000 (+0000)
Subject: RISC-V: Document `auipc' and `bitmanip' `type' attributes
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=833e651a76cbab26d18307fe761b609c0fa61439;p=test_jj.git

RISC-V: Document `auipc' and `bitmanip' `type' attributes

Document new `auipc' and `bitmanip' `type' attributes added respectively
with commit 88108b27dda9 ("RISC-V: Add sifive-7 pipeline description.")
and commit 283b1707f237 ("RISC-V: Implement instruction patterns for ZBA
extension.") but not listed so far.

	gcc/
	* config/riscv/riscv.md: Document `auipc' and `bitmanip' `type'
	attributes.
---

diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 0492392..b3c5bce 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -150,6 +150,7 @@
 ;; mfc		transfer from coprocessor
 ;; const	load constant
 ;; arith	integer arithmetic instructions
+;; auipc	integer addition to PC
 ;; logical      integer logical instructions
 ;; shift	integer shift instructions
 ;; slt		set less than instructions
@@ -167,6 +168,7 @@
 ;; multi	multiword sequence (or user asm statements)
 ;; nop		no operation
 ;; ghost	an instruction that produces no real code
+;; bitmanip	bit manipulation instructions
 (define_attr "type"
   "unknown,branch,jump,call,load,fpload,store,fpstore,
    mtc,mfc,const,arith,logical,shift,slt,imul,idiv,move,fmove,fadd,fmul,