From: M Henning Date: Sun, 30 Jan 2022 03:20:58 +0000 (-0500) Subject: nouveau: Skip cctl for atomic counters in tgsi X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=8313a9231c9a7e6f649cbd663d1cf2a7b0fbb91d;p=platform%2Fupstream%2Fmesa.git nouveau: Skip cctl for atomic counters in tgsi The tgsi path already marked all aliasing loads of atomic counters with CACHE_CG, so we don't need to emit a cctl. This patch uses the cache flag on the atomic to model whether the L1 cache needs the stale values to be flushed or not. Reviewed-by: Karol Herbst Part-of: --- diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp index 20b9ca8..d843d67 100644 --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp @@ -2962,6 +2962,10 @@ Converter::handleATOM(Value *dst0[4], DataType ty, uint16_t subOp) if (ind) insn->setIndirect(0, 1, ind); insn->subOp = subOp; + + if (tgsi.getSrc(0).getFile() == TGSI_FILE_BUFFER && + code->bufferAtomics[tgsi.getSrc(0).getIndex(0)]) + insn->cache = nv50_ir::CACHE_CG; } for (int c = 0; c < 4; ++c) if (dst0[c]) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp index fbdc1b8..18e2192 100644 --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp @@ -1708,6 +1708,10 @@ bool NVC0LoweringPass::handleATOMCctl(Instruction *atom) { // Flush L1 cache manually since atomics go directly to L2. This ensures // that any later CA reads retrieve the updated data. + + if (atom->cache != nv50_ir::CACHE_CA) + return false; + bld.setPosition(atom, true); Instruction *cctl = bld.mkOp1(OP_CCTL, TYPE_NONE, NULL, atom->getSrc(0));