From: Kenneth Graunke <kenneth@whitecape.org>
Date: Tue, 5 Jan 2016 09:53:57 +0000 (-0800)
Subject: i965: Explicitly write the "TR DS Cache Disable" bit at TCS EOT.
X-Git-Tag: upstream/17.1.0~12702
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=830b075e86e3e9af1bf12316d0f9d888a85a973b;p=platform%2Fupstream%2Fmesa.git

i965: Explicitly write the "TR DS Cache Disable" bit at TCS EOT.

Bit 0 of the Patch Header is "TR DS Cache Disable".  Setting that bit
disables the DS Cache for tessellator-output topologies resulting in
stitch-transition regions (but leaves it enabled for other cases).

We probably shouldn't leave this to chance - the URB could contain
garbage - which could result in the cache randomly being turned on
or off.

This patch makes the final EOT write 0 to the first DWord (which
only contains this one bit).  This ensures the cache is always on.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
---

diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp b/src/mesa/drivers/dri/i965/brw_vec4.cpp
index e7aec1f..e8bc2ec 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp
@@ -274,9 +274,9 @@ vec4_visitor::implied_mrf_writes(vec4_instruction *inst)
    case SHADER_OPCODE_INT_QUOTIENT:
    case SHADER_OPCODE_INT_REMAINDER:
    case SHADER_OPCODE_POW:
+   case TCS_OPCODE_THREAD_END:
       return 2;
    case VS_OPCODE_URB_WRITE:
-   case TCS_OPCODE_THREAD_END:
       return 1;
    case VS_OPCODE_PULL_CONSTANT_LOAD:
       return 2;
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
index 730be21..ee39777 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
@@ -980,15 +980,18 @@ generate_tcs_thread_end(struct brw_codegen *p, vec4_instruction *inst)
    brw_set_default_access_mode(p, BRW_ALIGN_1);
    brw_set_default_mask_control(p, BRW_MASK_DISABLE);
    brw_MOV(p, header, brw_imm_ud(0));
+   brw_MOV(p, get_element_ud(header, 5), brw_imm_ud(WRITEMASK_X << 8));
    brw_MOV(p, get_element_ud(header, 0),
            retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD));
+   brw_MOV(p, brw_message_reg(inst->base_mrf + 1), brw_imm_ud(0u));
    brw_pop_insn_state(p);
 
    brw_urb_WRITE(p,
                  brw_null_reg(), /* dest */
                  inst->base_mrf, /* starting mrf reg nr */
                  header,
-                 BRW_URB_WRITE_EOT | inst->urb_write_flags,
+                 BRW_URB_WRITE_EOT | BRW_URB_WRITE_OWORD |
+                 BRW_URB_WRITE_USE_CHANNEL_MASKS,
                  inst->mlen,
                  0,              /* response len */
                  0,              /* urb destination offset */
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_tcs.cpp b/src/mesa/drivers/dri/i965/brw_vec4_tcs.cpp
index 9b75f45..0d56356 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_tcs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_tcs.cpp
@@ -205,7 +205,7 @@ vec4_tcs_visitor::emit_thread_end()
 
    inst = emit(TCS_OPCODE_THREAD_END);
    inst->base_mrf = 14;
-   inst->mlen = 1;
+   inst->mlen = 2;
 }