From: Linus Torvalds <torvalds@linux-foundation.org>
Date: Fri, 28 Oct 2011 12:14:48 +0000 (-0700)
Subject: Merge branch 'x86-microcode-for-linus' of git://git.kernel.org/pub/scm/linux/kernel... 
X-Git-Tag: v3.2-rc1~140
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=8237eb946a1a23c600fb289cf8dd3b399b10604e;p=profile%2Fcommon%2Fkernel-common.git

Merge branch 'x86-microcode-for-linus' of git://git./linux/kernel/git/tip/tip

* 'x86-microcode-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  x86, microcode, AMD: Add microcode revision to /proc/cpuinfo
  x86, microcode: Correct microcode revision format
  coretemp: Get microcode revision from cpu_data
  x86, intel: Use c->microcode for Atom errata check
  x86, intel: Output microcode revision in /proc/cpuinfo
  x86, microcode: Don't request microcode from userspace unnecessarily

Fix up trivial conflicts in arch/x86/kernel/cpu/amd.c (conflict between
moving AMD BSP code to cpu_dev helper function and adding AMD microcode
revision to /proc/cpuinfo code)
---

8237eb946a1a23c600fb289cf8dd3b399b10604e
diff --cc arch/x86/kernel/cpu/amd.c
index 13c6ec8,d898fab..46ae4f6
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@@ -411,36 -410,10 +411,38 @@@ static void __cpuinit early_init_amd_mc
  #endif
  }
  
 +static void __cpuinit bsp_init_amd(struct cpuinfo_x86 *c)
 +{
 +	if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) {
 +
 +		if (c->x86 > 0x10 ||
 +		    (c->x86 == 0x10 && c->x86_model >= 0x2)) {
 +			u64 val;
 +
 +			rdmsrl(MSR_K7_HWCR, val);
 +			if (!(val & BIT(24)))
 +				printk(KERN_WARNING FW_BUG "TSC doesn't count "
 +					"with P0 frequency!\n");
 +		}
 +	}
 +
 +	if (c->x86 == 0x15) {
 +		unsigned long upperbit;
 +		u32 cpuid, assoc;
 +
 +		cpuid	 = cpuid_edx(0x80000005);
 +		assoc	 = cpuid >> 16 & 0xff;
 +		upperbit = ((cpuid >> 24) << 10) / assoc;
 +
 +		va_align.mask	  = (upperbit - 1) & PAGE_MASK;
 +		va_align.flags    = ALIGN_VA_32 | ALIGN_VA_64;
 +	}
 +}
 +
  static void __cpuinit early_init_amd(struct cpuinfo_x86 *c)
  {
+ 	u32 dummy;
+ 
  	early_init_amd_mc(c);
  
  	/*
@@@ -470,6 -443,25 +472,8 @@@
  			set_cpu_cap(c, X86_FEATURE_EXTD_APICID);
  	}
  #endif
+ 
+ 	rdmsr_safe(MSR_AMD64_PATCH_LEVEL, &c->microcode, &dummy);
 -
 -	/* We need to do the following only once */
 -	if (c != &boot_cpu_data)
 -		return;
 -
 -	if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) {
 -
 -		if (c->x86 > 0x10 ||
 -		    (c->x86 == 0x10 && c->x86_model >= 0x2)) {
 -			u64 val;
 -
 -			rdmsrl(MSR_K7_HWCR, val);
 -			if (!(val & BIT(24)))
 -				printk(KERN_WARNING FW_BUG "TSC doesn't count "
 -					"with P0 frequency!\n");
 -		}
 -	}
  }
  
  static void __cpuinit init_amd(struct cpuinfo_x86 *c)