From: Ezequiel Garcia Date: Wed, 12 Mar 2014 15:41:41 +0000 (-0300) Subject: clk: mvebu: Fix ratio register offset on A375 SoC X-Git-Tag: v3.15-rc1~72^2~38^2~2 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=8230a5ab435c6a0f395ff8fb190e53b563f06179;p=platform%2Fkernel%2Flinux-exynos.git clk: mvebu: Fix ratio register offset on A375 SoC This commit fixes the ratio register offset which is 0x4, as per the Armada 375 SoC specification. Signed-off-by: Ezequiel Garcia Link: https://lkml.kernel.org/r/1394638901-13368-2-git-send-email-ezequiel.garcia@free-electrons.com Signed-off-by: Jason Cooper --- diff --git a/drivers/clk/mvebu/clk-corediv.c b/drivers/clk/mvebu/clk-corediv.c index 4da6076..4af33ba 100644 --- a/drivers/clk/mvebu/clk-corediv.c +++ b/drivers/clk/mvebu/clk-corediv.c @@ -213,7 +213,7 @@ static const struct clk_corediv_soc_desc armada375_corediv_soc = { .set_rate = clk_corediv_set_rate, }, .ratio_reload = BIT(8), - .ratio_offset = 0x8, + .ratio_offset = 0x4, }; static void __init