From: Sander de Smalen Date: Mon, 9 Jul 2018 13:23:41 +0000 (+0000) Subject: [AArch64][SVE] Asm: Support for remaining shift instructions. X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=813b21e33a69d05efb65580ff56dd3aae6cfe9a6;p=platform%2Fupstream%2Fllvm.git [AArch64][SVE] Asm: Support for remaining shift instructions. This patch completes support for shifts, which include: - LSL - Logical Shift Left - LSLR - Logical Shift Left, Reversed form - LSR - Logical Shift Right - LSRR - Logical Shift Right, Reversed form - ASR - Arithmetic Shift Right - ASRR - Arithmetic Shift Right, Reversed form - ASRD - Arithmetic Shift Right for Divide In the following variants: - Predicated shift by immediate - ASR, LSL, LSR, ASRD e.g. asr z0.h, p0/m, z0.h, #1 (active lanes of z0 shifted by #1) - Unpredicated shift by immediate - ASR, LSL*, LSR* e.g. asr z0.h, z1.h, #1 (all lanes of z1 shifted by #1, stored in z0) - Predicated shift by vector - ASR, LSL*, LSR* e.g. asr z0.h, p0/m, z0.h, z1.h (active lanes of z0 shifted by z1, stored in z0) - Predicated shift by vector, reversed form - ASRR, LSLR, LSRR e.g. lslr z0.h, p0/m, z0.h, z1.h (active lanes of z1 shifted by z0, stored in z0) - Predicated shift left/right by wide vector - ASR, LSL, LSR e.g. lsl z0.h, p0/m, z0.h, z1.d (active lanes of z0 shifted by wide elements of vector z1) - Unpredicated shift left/right by wide vector - ASR, LSL, LSR e.g. lsl z0.h, z1.h, z2.d (all lanes of z1 shifted by wide elements of z2, stored in z0) *Variants added in previous patches. llvm-svn: 336547 --- diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td index 686bd0a..e2ed98b 100644 --- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td @@ -690,11 +690,31 @@ let Predicates = [HasSVE] in { defm INDEX_RI : sve_int_index_ri<"index">; defm INDEX_II : sve_int_index_ii<"index">; - defm LSR_ZZI : sve_int_bin_cons_shift_b_right<0b01, "lsr">; - defm LSL_ZZI : sve_int_bin_cons_shift_b_left< 0b11, "lsl">; - - defm LSR_ZPmZ : sve_int_bin_pred_shift_1<0b001, "lsr">; - defm LSL_ZPmZ : sve_int_bin_pred_shift_1<0b011, "lsl">; + // Unpredicated shifts + defm ASR_ZZI : sve_int_bin_cons_shift_imm_right<0b00, "asr">; + defm LSR_ZZI : sve_int_bin_cons_shift_imm_right<0b01, "lsr">; + defm LSL_ZZI : sve_int_bin_cons_shift_imm_left< 0b11, "lsl">; + + defm ASR_WIDE_ZZZ : sve_int_bin_cons_shift_wide<0b00, "asr">; + defm LSR_WIDE_ZZZ : sve_int_bin_cons_shift_wide<0b01, "lsr">; + defm LSL_WIDE_ZZZ : sve_int_bin_cons_shift_wide<0b11, "lsl">; + + // Predicated shifts + defm ASR_ZPmI : sve_int_bin_pred_shift_imm_right<0b000, "asr">; + defm LSR_ZPmI : sve_int_bin_pred_shift_imm_right<0b001, "lsr">; + defm LSL_ZPmI : sve_int_bin_pred_shift_imm_left< 0b011, "lsl">; + defm ASRD_ZPmI : sve_int_bin_pred_shift_imm_right<0b100, "asrd">; + + defm ASR_ZPmZ : sve_int_bin_pred_shift<0b000, "asr">; + defm LSR_ZPmZ : sve_int_bin_pred_shift<0b001, "lsr">; + defm LSL_ZPmZ : sve_int_bin_pred_shift<0b011, "lsl">; + defm ASRR_ZPmZ : sve_int_bin_pred_shift<0b100, "asrr">; + defm LSRR_ZPmZ : sve_int_bin_pred_shift<0b101, "lsrr">; + defm LSLR_ZPmZ : sve_int_bin_pred_shift<0b111, "lslr">; + + defm ASR_WIDE_ZPmZ : sve_int_bin_pred_shift_wide<0b000, "asr">; + defm LSR_WIDE_ZPmZ : sve_int_bin_pred_shift_wide<0b001, "lsr">; + defm LSL_WIDE_ZPmZ : sve_int_bin_pred_shift_wide<0b011, "lsl">; def FCVT_ZPmZ_StoH : sve_fp_2op_p_zd<0b1001000, "fcvt", ZPR32, ZPR16>; def FCVT_ZPmZ_HtoS : sve_fp_2op_p_zd<0b1001001, "fcvt", ZPR16, ZPR32>; diff --git a/llvm/lib/Target/AArch64/SVEInstrFormats.td b/llvm/lib/Target/AArch64/SVEInstrFormats.td index 6fd617f..cc6b548 100644 --- a/llvm/lib/Target/AArch64/SVEInstrFormats.td +++ b/llvm/lib/Target/AArch64/SVEInstrFormats.td @@ -1688,9 +1688,59 @@ multiclass sve_int_index_rr { // SVE Bitwise Shift - Predicated Group //===----------------------------------------------------------------------===// -class sve_int_bin_pred_shift_1 sz8_64, bits<3> opc, string asm, - ZPRRegOp zprty> -: I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty:$Zm), +class sve_int_bin_pred_shift_imm tsz8_64, bits<3> opc, string asm, + ZPRRegOp zprty, Operand immtype> +: I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, immtype:$imm), + asm, "\t$Zdn, $Pg/m, $_Zdn, $imm", + "", + []>, Sched<[]> { + bits<3> Pg; + bits<5> Zdn; + bits<6> imm; + let Inst{31-24} = 0b00000100; + let Inst{23-22} = tsz8_64{3-2}; + let Inst{21-19} = 0b000; + let Inst{18-16} = opc; + let Inst{15-13} = 0b100; + let Inst{12-10} = Pg; + let Inst{9-8} = tsz8_64{1-0}; + let Inst{7-5} = imm{2-0}; // imm3 + let Inst{4-0} = Zdn; + + let Constraints = "$Zdn = $_Zdn"; +} + +multiclass sve_int_bin_pred_shift_imm_left opc, string asm> { + def _B : sve_int_bin_pred_shift_imm<{0,0,0,1}, opc, asm, ZPR8, vecshiftL8>; + def _H : sve_int_bin_pred_shift_imm<{0,0,1,?}, opc, asm, ZPR16, vecshiftL16> { + let Inst{8} = imm{3}; + } + def _S : sve_int_bin_pred_shift_imm<{0,1,?,?}, opc, asm, ZPR32, vecshiftL32> { + let Inst{9-8} = imm{4-3}; + } + def _D : sve_int_bin_pred_shift_imm<{1,?,?,?}, opc, asm, ZPR64, vecshiftL64> { + let Inst{22} = imm{5}; + let Inst{9-8} = imm{4-3}; + } +} + +multiclass sve_int_bin_pred_shift_imm_right opc, string asm> { + def _B : sve_int_bin_pred_shift_imm<{0,0,0,1}, opc, asm, ZPR8, vecshiftR8>; + def _H : sve_int_bin_pred_shift_imm<{0,0,1,?}, opc, asm, ZPR16, vecshiftR16> { + let Inst{8} = imm{3}; + } + def _S : sve_int_bin_pred_shift_imm<{0,1,?,?}, opc, asm, ZPR32, vecshiftR32> { + let Inst{9-8} = imm{4-3}; + } + def _D : sve_int_bin_pred_shift_imm<{1,?,?,?}, opc, asm, ZPR64, vecshiftR64> { + let Inst{22} = imm{5}; + let Inst{9-8} = imm{4-3}; + } +} + +class sve_int_bin_pred_shift sz8_64, bit wide, bits<3> opc, + string asm, ZPRRegOp zprty, ZPRRegOp zprty2> +: I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty2:$Zm), asm, "\t$Zdn, $Pg/m, $_Zdn, $Zm", "", []>, Sched<[]> { @@ -1699,7 +1749,8 @@ class sve_int_bin_pred_shift_1 sz8_64, bits<3> opc, string asm, bits<5> Zm; let Inst{31-24} = 0b00000100; let Inst{23-22} = sz8_64; - let Inst{21-19} = 0b010; + let Inst{21-20} = 0b01; + let Inst{19} = wide; let Inst{18-16} = opc; let Inst{15-13} = 0b100; let Inst{12-10} = Pg; @@ -1709,19 +1760,49 @@ class sve_int_bin_pred_shift_1 sz8_64, bits<3> opc, string asm, let Constraints = "$Zdn = $_Zdn"; } -multiclass sve_int_bin_pred_shift_1 opc, string asm> { - def _B : sve_int_bin_pred_shift_1<0b00, opc, asm, ZPR8>; - def _H : sve_int_bin_pred_shift_1<0b01, opc, asm, ZPR16>; - def _S : sve_int_bin_pred_shift_1<0b10, opc, asm, ZPR32>; - def _D : sve_int_bin_pred_shift_1<0b11, opc, asm, ZPR64>; +multiclass sve_int_bin_pred_shift opc, string asm> { + def _B : sve_int_bin_pred_shift<0b00, 0b0, opc, asm, ZPR8, ZPR8>; + def _H : sve_int_bin_pred_shift<0b01, 0b0, opc, asm, ZPR16, ZPR16>; + def _S : sve_int_bin_pred_shift<0b10, 0b0, opc, asm, ZPR32, ZPR32>; + def _D : sve_int_bin_pred_shift<0b11, 0b0, opc, asm, ZPR64, ZPR64>; } +multiclass sve_int_bin_pred_shift_wide opc, string asm> { + def _B : sve_int_bin_pred_shift<0b00, 0b1, opc, asm, ZPR8, ZPR64>; + def _H : sve_int_bin_pred_shift<0b01, 0b1, opc, asm, ZPR16, ZPR64>; + def _S : sve_int_bin_pred_shift<0b10, 0b1, opc, asm, ZPR32, ZPR64>; +} //===----------------------------------------------------------------------===// -// SVE Shift by Immediate - Unpredicated Group +// SVE Shift - Unpredicated Group //===----------------------------------------------------------------------===// -class sve_int_bin_cons_shift_b tsz8_64, bits<2> opc, string asm, +class sve_int_bin_cons_shift_wide sz8_64, bits<2> opc, string asm, + ZPRRegOp zprty> +: I<(outs zprty:$Zd), (ins zprty:$Zn, ZPR64:$Zm), + asm, "\t$Zd, $Zn, $Zm", + "", + []>, Sched<[]> { + bits<5> Zd; + bits<5> Zm; + bits<5> Zn; + let Inst{31-24} = 0b00000100; + let Inst{23-22} = sz8_64; + let Inst{21} = 0b1; + let Inst{20-16} = Zm; + let Inst{15-12} = 0b1000; + let Inst{11-10} = opc; + let Inst{9-5} = Zn; + let Inst{4-0} = Zd; +} + +multiclass sve_int_bin_cons_shift_wide opc, string asm> { + def _B : sve_int_bin_cons_shift_wide<0b00, opc, asm, ZPR8>; + def _H : sve_int_bin_cons_shift_wide<0b01, opc, asm, ZPR16>; + def _S : sve_int_bin_cons_shift_wide<0b10, opc, asm, ZPR32>; +} + +class sve_int_bin_cons_shift_imm tsz8_64, bits<2> opc, string asm, ZPRRegOp zprty, Operand immtype> : I<(outs zprty:$Zd), (ins zprty:$Zn, immtype:$imm), asm, "\t$Zd, $Zn, $imm", @@ -1740,29 +1821,29 @@ class sve_int_bin_cons_shift_b tsz8_64, bits<2> opc, string asm, let Inst{4-0} = Zd; } -multiclass sve_int_bin_cons_shift_b_left opc, string asm> { - def _B : sve_int_bin_cons_shift_b<{0,0,0,1}, opc, asm, ZPR8, vecshiftL8>; - def _H : sve_int_bin_cons_shift_b<{0,0,1,?}, opc, asm, ZPR16, vecshiftL16> { +multiclass sve_int_bin_cons_shift_imm_left opc, string asm> { + def _B : sve_int_bin_cons_shift_imm<{0,0,0,1}, opc, asm, ZPR8, vecshiftL8>; + def _H : sve_int_bin_cons_shift_imm<{0,0,1,?}, opc, asm, ZPR16, vecshiftL16> { let Inst{19} = imm{3}; } - def _S : sve_int_bin_cons_shift_b<{0,1,?,?}, opc, asm, ZPR32, vecshiftL32> { + def _S : sve_int_bin_cons_shift_imm<{0,1,?,?}, opc, asm, ZPR32, vecshiftL32> { let Inst{20-19} = imm{4-3}; } - def _D : sve_int_bin_cons_shift_b<{1,?,?,?}, opc, asm, ZPR64, vecshiftL64> { + def _D : sve_int_bin_cons_shift_imm<{1,?,?,?}, opc, asm, ZPR64, vecshiftL64> { let Inst{22} = imm{5}; let Inst{20-19} = imm{4-3}; } } -multiclass sve_int_bin_cons_shift_b_right opc, string asm> { - def _B : sve_int_bin_cons_shift_b<{0,0,0,1}, opc, asm, ZPR8, vecshiftR8>; - def _H : sve_int_bin_cons_shift_b<{0,0,1,?}, opc, asm, ZPR16, vecshiftR16> { +multiclass sve_int_bin_cons_shift_imm_right opc, string asm> { + def _B : sve_int_bin_cons_shift_imm<{0,0,0,1}, opc, asm, ZPR8, vecshiftR8>; + def _H : sve_int_bin_cons_shift_imm<{0,0,1,?}, opc, asm, ZPR16, vecshiftR16> { let Inst{19} = imm{3}; } - def _S : sve_int_bin_cons_shift_b<{0,1,?,?}, opc, asm, ZPR32, vecshiftR32> { + def _S : sve_int_bin_cons_shift_imm<{0,1,?,?}, opc, asm, ZPR32, vecshiftR32> { let Inst{20-19} = imm{4-3}; } - def _D : sve_int_bin_cons_shift_b<{1,?,?,?}, opc, asm, ZPR64, vecshiftR64> { + def _D : sve_int_bin_cons_shift_imm<{1,?,?,?}, opc, asm, ZPR64, vecshiftR64> { let Inst{22} = imm{5}; let Inst{20-19} = imm{4-3}; } diff --git a/llvm/test/MC/AArch64/SVE/asr-diagnostics.s b/llvm/test/MC/AArch64/SVE/asr-diagnostics.s new file mode 100644 index 0000000..a481132 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE/asr-diagnostics.s @@ -0,0 +1,124 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s + +asr z30.b, z10.b, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8] +// CHECK-NEXT: asr z30.b, z10.b, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +asr z18.b, z27.b, #9 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8] +// CHECK-NEXT: asr z18.b, z27.b, #9 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +asr z18.b, p0/m, z28.b, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8] +// CHECK-NEXT: asr z18.b, p0/m, z28.b, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +asr z1.b, p0/m, z9.b, #9 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8] +// CHECK-NEXT: asr z1.b, p0/m, z9.b, #9 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +asr z26.h, z4.h, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16] +// CHECK-NEXT: asr z26.h, z4.h, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +asr z25.h, z10.h, #17 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16] +// CHECK-NEXT: asr z25.h, z10.h, #17 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +asr z21.h, p0/m, z2.h, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16] +// CHECK-NEXT: asr z21.h, p0/m, z2.h, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +asr z14.h, p0/m, z30.h, #17 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16] +// CHECK-NEXT: asr z14.h, p0/m, z30.h, #17 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +asr z17.s, z0.s, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32] +// CHECK-NEXT: asr z17.s, z0.s, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +asr z0.s, z15.s, #33 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32] +// CHECK-NEXT: asr z0.s, z15.s, #33 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +asr z6.s, p0/m, z12.s, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32] +// CHECK-NEXT: asr z6.s, p0/m, z12.s, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +asr z23.s, p0/m, z19.s, #33 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32] +// CHECK-NEXT: asr z23.s, p0/m, z19.s, #33 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +asr z4.d, z13.d, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 64] +// CHECK-NEXT: asr z4.d, z13.d, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +asr z26.d, z26.d, #65 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 64] +// CHECK-NEXT: asr z26.d, z26.d, #65 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +asr z3.d, p0/m, z24.d, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 64] +// CHECK-NEXT: asr z3.d, p0/m, z24.d, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +asr z25.d, p0/m, z16.d, #65 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 64] +// CHECK-NEXT: asr z25.d, p0/m, z16.d, #65 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Source and Destination Registers must match + +asr z0.b, p0/m, z1.b, z2.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: asr z0.b, p0/m, z1.b, z2.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +asr z0.b, p0/m, z1.b, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: asr z0.b, p0/m, z1.b, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Element sizes must match + +asr z0.b, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: asr z0.b, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +asr z0.b, p0/m, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: asr z0.b, p0/m, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +asr z0.b, p0/m, z0.b, z1.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: asr z0.b, p0/m, z0.b, z1.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// +// Predicate not in restricted predicate range + +asr z0.b, p8/m, z0.b, z1.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: asr z0.b, p8/m, z0.b, z1.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + diff --git a/llvm/test/MC/AArch64/SVE/asr.s b/llvm/test/MC/AArch64/SVE/asr.s new file mode 100644 index 0000000..7204a27 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE/asr.s @@ -0,0 +1,164 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +asr z0.b, z0.b, #1 +// CHECK-INST: asr z0.b, z0.b, #1 +// CHECK-ENCODING: [0x00,0x90,0x2f,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 90 2f 04 + +asr z31.b, z31.b, #8 +// CHECK-INST: asr z31.b, z31.b, #8 +// CHECK-ENCODING: [0xff,0x93,0x28,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 93 28 04 + +asr z0.h, z0.h, #1 +// CHECK-INST: asr z0.h, z0.h, #1 +// CHECK-ENCODING: [0x00,0x90,0x3f,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 90 3f 04 + +asr z31.h, z31.h, #16 +// CHECK-INST: asr z31.h, z31.h, #16 +// CHECK-ENCODING: [0xff,0x93,0x30,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 93 30 04 + +asr z0.s, z0.s, #1 +// CHECK-INST: asr z0.s, z0.s, #1 +// CHECK-ENCODING: [0x00,0x90,0x7f,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 90 7f 04 + +asr z31.s, z31.s, #32 +// CHECK-INST: asr z31.s, z31.s, #32 +// CHECK-ENCODING: [0xff,0x93,0x60,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 93 60 04 + +asr z0.d, z0.d, #1 +// CHECK-INST: asr z0.d, z0.d, #1 +// CHECK-ENCODING: [0x00,0x90,0xff,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 90 ff 04 + +asr z31.d, z31.d, #64 +// CHECK-INST: asr z31.d, z31.d, #64 +// CHECK-ENCODING: [0xff,0x93,0xa0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 93 a0 04 + +asr z0.b, p0/m, z0.b, #1 +// CHECK-INST: asr z0.b, p0/m, z0.b, #1 +// CHECK-ENCODING: [0xe0,0x81,0x00,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 81 00 04 + +asr z31.b, p0/m, z31.b, #8 +// CHECK-INST: asr z31.b, p0/m, z31.b, #8 +// CHECK-ENCODING: [0x1f,0x81,0x00,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 1f 81 00 04 + +asr z0.h, p0/m, z0.h, #1 +// CHECK-INST: asr z0.h, p0/m, z0.h, #1 +// CHECK-ENCODING: [0xe0,0x83,0x00,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 83 00 04 + +asr z31.h, p0/m, z31.h, #16 +// CHECK-INST: asr z31.h, p0/m, z31.h, #16 +// CHECK-ENCODING: [0x1f,0x82,0x00,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 1f 82 00 04 + +asr z0.s, p0/m, z0.s, #1 +// CHECK-INST: asr z0.s, p0/m, z0.s, #1 +// CHECK-ENCODING: [0xe0,0x83,0x40,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 83 40 04 + +asr z31.s, p0/m, z31.s, #32 +// CHECK-INST: asr z31.s, p0/m, z31.s, #32 +// CHECK-ENCODING: [0x1f,0x80,0x40,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 1f 80 40 04 + +asr z0.d, p0/m, z0.d, #1 +// CHECK-INST: asr z0.d, p0/m, z0.d, #1 +// CHECK-ENCODING: [0xe0,0x83,0xc0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 83 c0 04 + +asr z31.d, p0/m, z31.d, #64 +// CHECK-INST: asr z31.d, p0/m, z31.d, #64 +// CHECK-ENCODING: [0x1f,0x80,0x80,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 1f 80 80 04 + +asr z0.b, p0/m, z0.b, z0.b +// CHECK-INST: asr z0.b, p0/m, z0.b, z0.b +// CHECK-ENCODING: [0x00,0x80,0x10,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 80 10 04 + +asr z0.h, p0/m, z0.h, z0.h +// CHECK-INST: asr z0.h, p0/m, z0.h, z0.h +// CHECK-ENCODING: [0x00,0x80,0x50,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 80 50 04 + +asr z0.s, p0/m, z0.s, z0.s +// CHECK-INST: asr z0.s, p0/m, z0.s, z0.s +// CHECK-ENCODING: [0x00,0x80,0x90,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 80 90 04 + +asr z0.d, p0/m, z0.d, z0.d +// CHECK-INST: asr z0.d, p0/m, z0.d, z0.d +// CHECK-ENCODING: [0x00,0x80,0xd0,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 80 d0 04 + +asr z0.b, p0/m, z0.b, z1.d +// CHECK-INST: asr z0.b, p0/m, z0.b, z1.d +// CHECK-ENCODING: [0x20,0x80,0x18,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 80 18 04 + +asr z0.h, p0/m, z0.h, z1.d +// CHECK-INST: asr z0.h, p0/m, z0.h, z1.d +// CHECK-ENCODING: [0x20,0x80,0x58,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 80 58 04 + +asr z0.s, p0/m, z0.s, z1.d +// CHECK-INST: asr z0.s, p0/m, z0.s, z1.d +// CHECK-ENCODING: [0x20,0x80,0x98,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 80 98 04 + +asr z0.b, z1.b, z2.d +// CHECK-INST: asr z0.b, z1.b, z2.d +// CHECK-ENCODING: [0x20,0x80,0x22,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 80 22 04 + +asr z0.h, z1.h, z2.d +// CHECK-INST: asr z0.h, z1.h, z2.d +// CHECK-ENCODING: [0x20,0x80,0x62,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 80 62 04 + +asr z0.s, z1.s, z2.d +// CHECK-INST: asr z0.s, z1.s, z2.d +// CHECK-ENCODING: [0x20,0x80,0xa2,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 80 a2 04 diff --git a/llvm/test/MC/AArch64/SVE/asrd-diagnostics.s b/llvm/test/MC/AArch64/SVE/asrd-diagnostics.s new file mode 100644 index 0000000..80bedc1 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE/asrd-diagnostics.s @@ -0,0 +1,41 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s + +asrd z18.b, p0/m, z28.b, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8] +// CHECK-NEXT: asrd z18.b, p0/m, z28.b, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +asrd z1.b, p0/m, z9.b, #9 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8] +// CHECK-NEXT: asrd z1.b, p0/m, z9.b, #9 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +asrd z21.h, p0/m, z2.h, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16] +// CHECK-NEXT: asrd z21.h, p0/m, z2.h, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +asrd z14.h, p0/m, z30.h, #17 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16] +// CHECK-NEXT: asrd z14.h, p0/m, z30.h, #17 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +asrd z6.s, p0/m, z12.s, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32] +// CHECK-NEXT: asrd z6.s, p0/m, z12.s, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +asrd z23.s, p0/m, z19.s, #33 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32] +// CHECK-NEXT: asrd z23.s, p0/m, z19.s, #33 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +asrd z3.d, p0/m, z24.d, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 64] +// CHECK-NEXT: asrd z3.d, p0/m, z24.d, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +asrd z25.d, p0/m, z16.d, #65 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 64] +// CHECK-NEXT: asrd z25.d, p0/m, z16.d, #65 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/asrd.s b/llvm/test/MC/AArch64/SVE/asrd.s new file mode 100644 index 0000000..6980551 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE/asrd.s @@ -0,0 +1,56 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +asrd z0.b, p0/m, z0.b, #1 +// CHECK-INST: asrd z0.b, p0/m, z0.b, #1 +// CHECK-ENCODING: [0xe0,0x81,0x04,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 81 04 04 + +asrd z31.b, p0/m, z31.b, #8 +// CHECK-INST: asrd z31.b, p0/m, z31.b, #8 +// CHECK-ENCODING: [0x1f,0x81,0x04,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 1f 81 04 04 + +asrd z0.h, p0/m, z0.h, #1 +// CHECK-INST: asrd z0.h, p0/m, z0.h, #1 +// CHECK-ENCODING: [0xe0,0x83,0x04,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 83 04 04 + +asrd z31.h, p0/m, z31.h, #16 +// CHECK-INST: asrd z31.h, p0/m, z31.h, #16 +// CHECK-ENCODING: [0x1f,0x82,0x04,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 1f 82 04 04 + +asrd z0.s, p0/m, z0.s, #1 +// CHECK-INST: asrd z0.s, p0/m, z0.s, #1 +// CHECK-ENCODING: [0xe0,0x83,0x44,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 83 44 04 + +asrd z31.s, p0/m, z31.s, #32 +// CHECK-INST: asrd z31.s, p0/m, z31.s, #32 +// CHECK-ENCODING: [0x1f,0x80,0x44,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 1f 80 44 04 + +asrd z0.d, p0/m, z0.d, #1 +// CHECK-INST: asrd z0.d, p0/m, z0.d, #1 +// CHECK-ENCODING: [0xe0,0x83,0xc4,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 83 c4 04 + +asrd z31.d, p0/m, z31.d, #64 +// CHECK-INST: asrd z31.d, p0/m, z31.d, #64 +// CHECK-ENCODING: [0x1f,0x80,0x84,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 1f 80 84 04 diff --git a/llvm/test/MC/AArch64/SVE/asrr-diagnostics.s b/llvm/test/MC/AArch64/SVE/asrr-diagnostics.s new file mode 100644 index 0000000..3ee157e --- /dev/null +++ b/llvm/test/MC/AArch64/SVE/asrr-diagnostics.s @@ -0,0 +1,21 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s + +asrr z0.b, p8/m, z0.b, z0.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: asrr z0.b, p8/m, z0.b, z0.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +asrr z0.b, p0/m, z0.b, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: asrr z0.b, p0/m, z0.b, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +asrr z0.h, p0/m, z0.h, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: asrr z0.h, p0/m, z0.h, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +asrr z0.s, p0/m, z0.s, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: asrr z0.s, p0/m, z0.s, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/asrr.s b/llvm/test/MC/AArch64/SVE/asrr.s new file mode 100644 index 0000000..e7f7cc5 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE/asrr.s @@ -0,0 +1,32 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +asrr z0.b, p0/m, z0.b, z0.b +// CHECK-INST: asrr z0.b, p0/m, z0.b, z0.b +// CHECK-ENCODING: [0x00,0x80,0x14,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 80 14 04 + +asrr z0.h, p0/m, z0.h, z0.h +// CHECK-INST: asrr z0.h, p0/m, z0.h, z0.h +// CHECK-ENCODING: [0x00,0x80,0x54,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 80 54 04 + +asrr z0.s, p0/m, z0.s, z0.s +// CHECK-INST: asrr z0.s, p0/m, z0.s, z0.s +// CHECK-ENCODING: [0x00,0x80,0x94,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 80 94 04 + +asrr z0.d, p0/m, z0.d, z0.d +// CHECK-INST: asrr z0.d, p0/m, z0.d, z0.d +// CHECK-ENCODING: [0x00,0x80,0xd4,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 80 d4 04 diff --git a/llvm/test/MC/AArch64/SVE/lsl-diagnostics.s b/llvm/test/MC/AArch64/SVE/lsl-diagnostics.s index 255f4f9..067acf9 100644 --- a/llvm/test/MC/AArch64/SVE/lsl-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/lsl-diagnostics.s @@ -10,6 +10,16 @@ lsl z1.b, z9.b, #8 // CHECK-NEXT: lsl z1.b, z9.b, #8 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: +lsl z18.b, p0/m, z28.b, #-1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7] +// CHECK-NEXT: lsl z18.b, p0/m, z28.b, #-1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +lsl z1.b, p0/m, z9.b, #8 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7] +// CHECK-NEXT: lsl z1.b, p0/m, z9.b, #8 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + lsl z21.h, z2.h, #-1 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 15] // CHECK-NEXT: lsl z21.h, z2.h, #-1 @@ -20,6 +30,16 @@ lsl z14.h, z30.h, #16 // CHECK-NEXT: lsl z14.h, z30.h, #16 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: +lsl z21.h, p0/m, z2.h, #-1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 15] +// CHECK-NEXT: lsl z21.h, p0/m, z2.h, #-1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +lsl z14.h, p0/m, z30.h, #16 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 15] +// CHECK-NEXT: lsl z14.h, p0/m, z30.h, #16 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + lsl z6.s, z12.s, #-1 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31] // CHECK-NEXT: lsl z6.s, z12.s, #-1 @@ -30,6 +50,16 @@ lsl z23.s, z19.s, #32 // CHECK-NEXT: lsl z23.s, z19.s, #32 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: +lsl z6.s, p0/m, z12.s, #-1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31] +// CHECK-NEXT: lsl z6.s, p0/m, z12.s, #-1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +lsl z23.s, p0/m, z19.s, #32 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31] +// CHECK-NEXT: lsl z23.s, p0/m, z19.s, #32 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + lsl z3.d, z24.d, #-1 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 63] // CHECK-NEXT: lsl z3.d, z24.d, #-1 @@ -40,19 +70,52 @@ lsl z25.d, z16.d, #64 // CHECK-NEXT: lsl z25.d, z16.d, #64 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: +lsl z3.d, p0/m, z24.d, #-1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 63] +// CHECK-NEXT: lsl z3.d, p0/m, z24.d, #-1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +lsl z25.d, p0/m, z16.d, #64 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 63] +// CHECK-NEXT: lsl z25.d, p0/m, z16.d, #64 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// // Source and Destination Registers must match + lsl z0.b, p0/m, z1.b, z2.b // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register // CHECK-NEXT: lsl z0.b, p0/m, z1.b, z2.b // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: +lsl z0.b, p0/m, z1.b, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: lsl z0.b, p0/m, z1.b, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// // Element sizes must match + +lsl z0.b, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: lsl z0.b, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +lsl z0.b, p0/m, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: lsl z0.b, p0/m, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + lsl z0.b, p0/m, z0.b, z1.h // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: lsl z0.b, p0/m, z0.b, z1.h // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: +// --------------------------------------------------------------------------// // Predicate not in restricted predicate range + lsl z0.b, p8/m, z0.b, z1.b // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK-NEXT: lsl z0.b, p8/m, z0.b, z1.b diff --git a/llvm/test/MC/AArch64/SVE/lsl.s b/llvm/test/MC/AArch64/SVE/lsl.s index c5d8482..0e8820e 100644 --- a/llvm/test/MC/AArch64/SVE/lsl.s +++ b/llvm/test/MC/AArch64/SVE/lsl.s @@ -8,73 +8,157 @@ // RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN lsl z0.b, z0.b, #0 -// CHECK-INST: lsl z0.b, z0.b, #0 +// CHECK-INST: lsl z0.b, z0.b, #0 // CHECK-ENCODING: [0x00,0x9c,0x28,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 00 9c 28 04 lsl z31.b, z31.b, #7 -// CHECK-INST: lsl z31.b, z31.b, #7 +// CHECK-INST: lsl z31.b, z31.b, #7 // CHECK-ENCODING: [0xff,0x9f,0x2f,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: ff 9f 2f 04 lsl z0.h, z0.h, #0 -// CHECK-INST: lsl z0.h, z0.h, #0 +// CHECK-INST: lsl z0.h, z0.h, #0 // CHECK-ENCODING: [0x00,0x9c,0x30,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 00 9c 30 04 lsl z31.h, z31.h, #15 -// CHECK-INST: lsl z31.h, z31.h, #15 +// CHECK-INST: lsl z31.h, z31.h, #15 // CHECK-ENCODING: [0xff,0x9f,0x3f,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: ff 9f 3f 04 lsl z0.s, z0.s, #0 -// CHECK-INST: lsl z0.s, z0.s, #0 +// CHECK-INST: lsl z0.s, z0.s, #0 // CHECK-ENCODING: [0x00,0x9c,0x60,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 00 9c 60 04 lsl z31.s, z31.s, #31 -// CHECK-INST: lsl z31.s, z31.s, #31 +// CHECK-INST: lsl z31.s, z31.s, #31 // CHECK-ENCODING: [0xff,0x9f,0x7f,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: ff 9f 7f 04 lsl z0.d, z0.d, #0 -// CHECK-INST: lsl z0.d, z0.d, #0 +// CHECK-INST: lsl z0.d, z0.d, #0 // CHECK-ENCODING: [0x00,0x9c,0xa0,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 00 9c a0 04 lsl z31.d, z31.d, #63 -// CHECK-INST: lsl z31.d, z31.d, #63 +// CHECK-INST: lsl z31.d, z31.d, #63 // CHECK-ENCODING: [0xff,0x9f,0xff,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: ff 9f ff 04 +lsl z0.b, p0/m, z0.b, #0 +// CHECK-INST: lsl z0.b, p0/m, z0.b, #0 +// CHECK-ENCODING: [0x00,0x81,0x03,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 81 03 04 + +lsl z31.b, p0/m, z31.b, #7 +// CHECK-INST: lsl z31.b, p0/m, z31.b, #7 +// CHECK-ENCODING: [0xff,0x81,0x03,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 81 03 04 + +lsl z0.h, p0/m, z0.h, #0 +// CHECK-INST: lsl z0.h, p0/m, z0.h, #0 +// CHECK-ENCODING: [0x00,0x82,0x03,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 82 03 04 + +lsl z31.h, p0/m, z31.h, #15 +// CHECK-INST: lsl z31.h, p0/m, z31.h, #15 +// CHECK-ENCODING: [0xff,0x83,0x03,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 83 03 04 + +lsl z0.s, p0/m, z0.s, #0 +// CHECK-INST: lsl z0.s, p0/m, z0.s, #0 +// CHECK-ENCODING: [0x00,0x80,0x43,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 80 43 04 + +lsl z31.s, p0/m, z31.s, #31 +// CHECK-INST: lsl z31.s, p0/m, z31.s, #31 +// CHECK-ENCODING: [0xff,0x83,0x43,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 83 43 04 + +lsl z0.d, p0/m, z0.d, #0 +// CHECK-INST: lsl z0.d, p0/m, z0.d, #0 +// CHECK-ENCODING: [0x00,0x80,0x83,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 80 83 04 + +lsl z31.d, p0/m, z31.d, #63 +// CHECK-INST: lsl z31.d, p0/m, z31.d, #63 +// CHECK-ENCODING: [0xff,0x83,0xc3,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: ff 83 c3 04 + lsl z0.b, p0/m, z0.b, z0.b -// CHECK-INST: lsl z0.b, p0/m, z0.b, z0.b +// CHECK-INST: lsl z0.b, p0/m, z0.b, z0.b // CHECK-ENCODING: [0x00,0x80,0x13,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 00 80 13 04 lsl z0.h, p0/m, z0.h, z0.h -// CHECK-INST: lsl z0.h, p0/m, z0.h, z0.h +// CHECK-INST: lsl z0.h, p0/m, z0.h, z0.h // CHECK-ENCODING: [0x00,0x80,0x53,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 00 80 53 04 lsl z0.s, p0/m, z0.s, z0.s -// CHECK-INST: lsl z0.s, p0/m, z0.s, z0.s +// CHECK-INST: lsl z0.s, p0/m, z0.s, z0.s // CHECK-ENCODING: [0x00,0x80,0x93,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 00 80 93 04 lsl z0.d, p0/m, z0.d, z0.d -// CHECK-INST: lsl z0.d, p0/m, z0.d, z0.d +// CHECK-INST: lsl z0.d, p0/m, z0.d, z0.d // CHECK-ENCODING: [0x00,0x80,0xd3,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 00 80 d3 04 + +lsl z0.b, p0/m, z0.b, z1.d +// CHECK-INST: lsl z0.b, p0/m, z0.b, z1.d +// CHECK-ENCODING: [0x20,0x80,0x1b,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 80 1b 04 + +lsl z0.h, p0/m, z0.h, z1.d +// CHECK-INST: lsl z0.h, p0/m, z0.h, z1.d +// CHECK-ENCODING: [0x20,0x80,0x5b,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 80 5b 04 + +lsl z0.s, p0/m, z0.s, z1.d +// CHECK-INST: lsl z0.s, p0/m, z0.s, z1.d +// CHECK-ENCODING: [0x20,0x80,0x9b,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 80 9b 04 + +lsl z0.b, z1.b, z2.d +// CHECK-INST: lsl z0.b, z1.b, z2.d +// CHECK-ENCODING: [0x20,0x8c,0x22,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 8c 22 04 + +lsl z0.h, z1.h, z2.d +// CHECK-INST: lsl z0.h, z1.h, z2.d +// CHECK-ENCODING: [0x20,0x8c,0x62,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 8c 62 04 + +lsl z0.s, z1.s, z2.d +// CHECK-INST: lsl z0.s, z1.s, z2.d +// CHECK-ENCODING: [0x20,0x8c,0xa2,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 8c a2 04 diff --git a/llvm/test/MC/AArch64/SVE/lslr-diagnostics.s b/llvm/test/MC/AArch64/SVE/lslr-diagnostics.s new file mode 100644 index 0000000..431b3ab --- /dev/null +++ b/llvm/test/MC/AArch64/SVE/lslr-diagnostics.s @@ -0,0 +1,21 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s + +lslr z0.b, p8/m, z0.b, z0.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: lslr z0.b, p8/m, z0.b, z0.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +lslr z0.b, p0/m, z0.b, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: lslr z0.b, p0/m, z0.b, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +lslr z0.h, p0/m, z0.h, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: lslr z0.h, p0/m, z0.h, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +lslr z0.s, p0/m, z0.s, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: lslr z0.s, p0/m, z0.s, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/lslr.s b/llvm/test/MC/AArch64/SVE/lslr.s new file mode 100644 index 0000000..ad8941f --- /dev/null +++ b/llvm/test/MC/AArch64/SVE/lslr.s @@ -0,0 +1,32 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +lslr z0.b, p0/m, z0.b, z0.b +// CHECK-INST: lslr z0.b, p0/m, z0.b, z0.b +// CHECK-ENCODING: [0x00,0x80,0x17,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 80 17 04 + +lslr z0.h, p0/m, z0.h, z0.h +// CHECK-INST: lslr z0.h, p0/m, z0.h, z0.h +// CHECK-ENCODING: [0x00,0x80,0x57,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 80 57 04 + +lslr z0.s, p0/m, z0.s, z0.s +// CHECK-INST: lslr z0.s, p0/m, z0.s, z0.s +// CHECK-ENCODING: [0x00,0x80,0x97,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 80 97 04 + +lslr z0.d, p0/m, z0.d, z0.d +// CHECK-INST: lslr z0.d, p0/m, z0.d, z0.d +// CHECK-ENCODING: [0x00,0x80,0xd7,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 80 d7 04 diff --git a/llvm/test/MC/AArch64/SVE/lsr-diagnostics.s b/llvm/test/MC/AArch64/SVE/lsr-diagnostics.s index 3b35323..77ad88d 100644 --- a/llvm/test/MC/AArch64/SVE/lsr-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/lsr-diagnostics.s @@ -10,6 +10,16 @@ lsr z18.b, z27.b, #9 // CHECK-NEXT: lsr z18.b, z27.b, #9 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: +lsr z18.b, p0/m, z28.b, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8] +// CHECK-NEXT: lsr z18.b, p0/m, z28.b, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +lsr z1.b, p0/m, z9.b, #9 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8] +// CHECK-NEXT: lsr z1.b, p0/m, z9.b, #9 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + lsr z26.h, z4.h, #0 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16] // CHECK-NEXT: lsr z26.h, z4.h, #0 @@ -20,6 +30,16 @@ lsr z25.h, z10.h, #17 // CHECK-NEXT: lsr z25.h, z10.h, #17 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: +lsr z21.h, p0/m, z2.h, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16] +// CHECK-NEXT: lsr z21.h, p0/m, z2.h, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +lsr z14.h, p0/m, z30.h, #17 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16] +// CHECK-NEXT: lsr z14.h, p0/m, z30.h, #17 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + lsr z17.s, z0.s, #0 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32] // CHECK-NEXT: lsr z17.s, z0.s, #0 @@ -30,6 +50,16 @@ lsr z0.s, z15.s, #33 // CHECK-NEXT: lsr z0.s, z15.s, #33 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: +lsr z6.s, p0/m, z12.s, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32] +// CHECK-NEXT: lsr z6.s, p0/m, z12.s, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +lsr z23.s, p0/m, z19.s, #33 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32] +// CHECK-NEXT: lsr z23.s, p0/m, z19.s, #33 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + lsr z4.d, z13.d, #0 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 64] // CHECK-NEXT: lsr z4.d, z13.d, #0 @@ -40,19 +70,53 @@ lsr z26.d, z26.d, #65 // CHECK-NEXT: lsr z26.d, z26.d, #65 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: +lsr z3.d, p0/m, z24.d, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 64] +// CHECK-NEXT: lsr z3.d, p0/m, z24.d, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +lsr z25.d, p0/m, z16.d, #65 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 64] +// CHECK-NEXT: lsr z25.d, p0/m, z16.d, #65 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// // Source and Destination Registers must match + lsr z0.b, p0/m, z1.b, z2.b // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register // CHECK-NEXT: lsr z0.b, p0/m, z1.b, z2.b // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: +lsr z0.b, p0/m, z1.b, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: lsr z0.b, p0/m, z1.b, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// --------------------------------------------------------------------------// // Element sizes must match + +lsr z0.b, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: lsr z0.b, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +lsr z0.b, p0/m, z0.d, z1.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: lsr z0.b, p0/m, z0.d, z1.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + lsr z0.b, p0/m, z0.b, z1.h // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK-NEXT: lsr z0.b, p0/m, z0.b, z1.h // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// // Predicate not in restricted predicate range + lsr z0.b, p8/m, z0.b, z1.b // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. // CHECK-NEXT: lsr z0.b, p8/m, z0.b, z1.b diff --git a/llvm/test/MC/AArch64/SVE/lsr.s b/llvm/test/MC/AArch64/SVE/lsr.s index fcb0a23..9ef6623 100644 --- a/llvm/test/MC/AArch64/SVE/lsr.s +++ b/llvm/test/MC/AArch64/SVE/lsr.s @@ -7,74 +7,158 @@ // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ // RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN -lsr z0.b, z0.b, #8 -// CHECK-INST: lsr z0.b, z0.b, #8 -// CHECK-ENCODING: [0x00,0x94,0x28,0x04] +lsr z0.b, z0.b, #1 +// CHECK-INST: lsr z0.b, z0.b, #1 +// CHECK-ENCODING: [0x00,0x94,0x2f,0x04] // CHECK-ERROR: instruction requires: sve -// CHECK-UNKNOWN: 00 94 28 04 +// CHECK-UNKNOWN: 00 94 2f 04 -lsr z31.b, z31.b, #1 -// CHECK-INST: lsr z31.b, z31.b, #1 -// CHECK-ENCODING: [0xff,0x97,0x2f,0x04] +lsr z31.b, z31.b, #8 +// CHECK-INST: lsr z31.b, z31.b, #8 +// CHECK-ENCODING: [0xff,0x97,0x28,0x04] // CHECK-ERROR: instruction requires: sve -// CHECK-UNKNOWN: ff 97 2f 04 +// CHECK-UNKNOWN: ff 97 28 04 -lsr z0.h, z0.h, #16 -// CHECK-INST: lsr z0.h, z0.h, #16 -// CHECK-ENCODING: [0x00,0x94,0x30,0x04] +lsr z0.h, z0.h, #1 +// CHECK-INST: lsr z0.h, z0.h, #1 +// CHECK-ENCODING: [0x00,0x94,0x3f,0x04] // CHECK-ERROR: instruction requires: sve -// CHECK-UNKNOWN: 00 94 30 04 +// CHECK-UNKNOWN: 00 94 3f 04 -lsr z31.h, z31.h, #1 -// CHECK-INST: lsr z31.h, z31.h, #1 -// CHECK-ENCODING: [0xff,0x97,0x3f,0x04] +lsr z31.h, z31.h, #16 +// CHECK-INST: lsr z31.h, z31.h, #16 +// CHECK-ENCODING: [0xff,0x97,0x30,0x04] // CHECK-ERROR: instruction requires: sve -// CHECK-UNKNOWN: ff 97 3f 04 +// CHECK-UNKNOWN: ff 97 30 04 -lsr z0.s, z0.s, #32 -// CHECK-INST: lsr z0.s, z0.s, #32 -// CHECK-ENCODING: [0x00,0x94,0x60,0x04] +lsr z0.s, z0.s, #1 +// CHECK-INST: lsr z0.s, z0.s, #1 +// CHECK-ENCODING: [0x00,0x94,0x7f,0x04] // CHECK-ERROR: instruction requires: sve -// CHECK-UNKNOWN: 00 94 60 04 +// CHECK-UNKNOWN: 00 94 7f 04 -lsr z31.s, z31.s, #1 -// CHECK-INST: lsr z31.s, z31.s, #1 -// CHECK-ENCODING: [0xff,0x97,0x7f,0x04] +lsr z31.s, z31.s, #32 +// CHECK-INST: lsr z31.s, z31.s, #32 +// CHECK-ENCODING: [0xff,0x97,0x60,0x04] // CHECK-ERROR: instruction requires: sve -// CHECK-UNKNOWN: ff 97 7f 04 +// CHECK-UNKNOWN: ff 97 60 04 -lsr z0.d, z0.d, #64 -// CHECK-INST: lsr z0.d, z0.d, #64 -// CHECK-ENCODING: [0x00,0x94,0xa0,0x04] +lsr z0.d, z0.d, #1 +// CHECK-INST: lsr z0.d, z0.d, #1 +// CHECK-ENCODING: [0x00,0x94,0xff,0x04] // CHECK-ERROR: instruction requires: sve -// CHECK-UNKNOWN: 00 94 a0 04 +// CHECK-UNKNOWN: 00 94 ff 04 -lsr z31.d, z31.d, #1 -// CHECK-INST: lsr z31.d, z31.d, #1 -// CHECK-ENCODING: [0xff,0x97,0xff,0x04] +lsr z31.d, z31.d, #64 +// CHECK-INST: lsr z31.d, z31.d, #64 +// CHECK-ENCODING: [0xff,0x97,0xa0,0x04] // CHECK-ERROR: instruction requires: sve -// CHECK-UNKNOWN: ff 97 ff 04 +// CHECK-UNKNOWN: ff 97 a0 04 + +lsr z0.b, p0/m, z0.b, #1 +// CHECK-INST: lsr z0.b, p0/m, z0.b, #1 +// CHECK-ENCODING: [0xe0,0x81,0x01,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 81 01 04 + +lsr z31.b, p0/m, z31.b, #8 +// CHECK-INST: lsr z31.b, p0/m, z31.b, #8 +// CHECK-ENCODING: [0x1f,0x81,0x01,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 1f 81 01 04 + +lsr z0.h, p0/m, z0.h, #1 +// CHECK-INST: lsr z0.h, p0/m, z0.h, #1 +// CHECK-ENCODING: [0xe0,0x83,0x01,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 83 01 04 + +lsr z31.h, p0/m, z31.h, #16 +// CHECK-INST: lsr z31.h, p0/m, z31.h, #16 +// CHECK-ENCODING: [0x1f,0x82,0x01,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 1f 82 01 04 + +lsr z0.s, p0/m, z0.s, #1 +// CHECK-INST: lsr z0.s, p0/m, z0.s, #1 +// CHECK-ENCODING: [0xe0,0x83,0x41,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 83 41 04 + +lsr z31.s, p0/m, z31.s, #32 +// CHECK-INST: lsr z31.s, p0/m, z31.s, #32 +// CHECK-ENCODING: [0x1f,0x80,0x41,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 1f 80 41 04 + +lsr z0.d, p0/m, z0.d, #1 +// CHECK-INST: lsr z0.d, p0/m, z0.d, #1 +// CHECK-ENCODING: [0xe0,0x83,0xc1,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: e0 83 c1 04 + +lsr z31.d, p0/m, z31.d, #64 +// CHECK-INST: lsr z31.d, p0/m, z31.d, #64 +// CHECK-ENCODING: [0x1f,0x80,0x81,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 1f 80 81 04 lsr z0.b, p0/m, z0.b, z0.b -// CHECK-INST: lsr z0.b, p0/m, z0.b, z0.b +// CHECK-INST: lsr z0.b, p0/m, z0.b, z0.b // CHECK-ENCODING: [0x00,0x80,0x11,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 00 80 11 04 lsr z0.h, p0/m, z0.h, z0.h -// CHECK-INST: lsr z0.h, p0/m, z0.h, z0.h +// CHECK-INST: lsr z0.h, p0/m, z0.h, z0.h // CHECK-ENCODING: [0x00,0x80,0x51,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 00 80 51 04 lsr z0.s, p0/m, z0.s, z0.s -// CHECK-INST: lsr z0.s, p0/m, z0.s, z0.s +// CHECK-INST: lsr z0.s, p0/m, z0.s, z0.s // CHECK-ENCODING: [0x00,0x80,0x91,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 00 80 91 04 lsr z0.d, p0/m, z0.d, z0.d -// CHECK-INST: lsr z0.d, p0/m, z0.d, z0.d +// CHECK-INST: lsr z0.d, p0/m, z0.d, z0.d // CHECK-ENCODING: [0x00,0x80,0xd1,0x04] // CHECK-ERROR: instruction requires: sve // CHECK-UNKNOWN: 00 80 d1 04 + +lsr z0.b, p0/m, z0.b, z1.d +// CHECK-INST: lsr z0.b, p0/m, z0.b, z1.d +// CHECK-ENCODING: [0x20,0x80,0x19,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 80 19 04 + +lsr z0.h, p0/m, z0.h, z1.d +// CHECK-INST: lsr z0.h, p0/m, z0.h, z1.d +// CHECK-ENCODING: [0x20,0x80,0x59,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 80 59 04 + +lsr z0.s, p0/m, z0.s, z1.d +// CHECK-INST: lsr z0.s, p0/m, z0.s, z1.d +// CHECK-ENCODING: [0x20,0x80,0x99,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 80 99 04 + +lsr z0.b, z1.b, z2.d +// CHECK-INST: lsr z0.b, z1.b, z2.d +// CHECK-ENCODING: [0x20,0x84,0x22,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 84 22 04 + +lsr z0.h, z1.h, z2.d +// CHECK-INST: lsr z0.h, z1.h, z2.d +// CHECK-ENCODING: [0x20,0x84,0x62,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 84 62 04 + +lsr z0.s, z1.s, z2.d +// CHECK-INST: lsr z0.s, z1.s, z2.d +// CHECK-ENCODING: [0x20,0x84,0xa2,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 20 84 a2 04 diff --git a/llvm/test/MC/AArch64/SVE/lsrr-diagnostics.s b/llvm/test/MC/AArch64/SVE/lsrr-diagnostics.s new file mode 100644 index 0000000..8aaf464 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE/lsrr-diagnostics.s @@ -0,0 +1,21 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s + +lsrr z0.b, p8/m, z0.b, z0.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. +// CHECK-NEXT: lsrr z0.b, p8/m, z0.b, z0.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +lsrr z0.b, p0/m, z0.b, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: lsrr z0.b, p0/m, z0.b, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +lsrr z0.h, p0/m, z0.h, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: lsrr z0.h, p0/m, z0.h, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +lsrr z0.s, p0/m, z0.s, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: lsrr z0.s, p0/m, z0.s, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/lsrr.s b/llvm/test/MC/AArch64/SVE/lsrr.s new file mode 100644 index 0000000..a6bca70 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE/lsrr.s @@ -0,0 +1,32 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +lsrr z0.b, p0/m, z0.b, z0.b +// CHECK-INST: lsrr z0.b, p0/m, z0.b, z0.b +// CHECK-ENCODING: [0x00,0x80,0x15,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 80 15 04 + +lsrr z0.h, p0/m, z0.h, z0.h +// CHECK-INST: lsrr z0.h, p0/m, z0.h, z0.h +// CHECK-ENCODING: [0x00,0x80,0x55,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 80 55 04 + +lsrr z0.s, p0/m, z0.s, z0.s +// CHECK-INST: lsrr z0.s, p0/m, z0.s, z0.s +// CHECK-ENCODING: [0x00,0x80,0x95,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 80 95 04 + +lsrr z0.d, p0/m, z0.d, z0.d +// CHECK-INST: lsrr z0.d, p0/m, z0.d, z0.d +// CHECK-ENCODING: [0x00,0x80,0xd5,0x04] +// CHECK-ERROR: instruction requires: sve +// CHECK-UNKNOWN: 00 80 d5 04