From: Marina Yatsina <marina.yatsina@intel.com>
Date: Mon, 22 Jan 2018 15:31:05 +0000 (+0000)
Subject: Fix bug in commit 323096 exposed by test in test-suite-verify-machineinstrs-x86_64h-O3
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=811523cc08b5b17768ff9427691dfb70a068dbbf;p=platform%2Fupstream%2Fllvm.git

Fix bug in commit 323096 exposed by test in test-suite-verify-machineinstrs-x86_64h-O3

Change-Id: I0a4b10d0d6c8de606d989c567ec07944ae283a87
llvm-svn: 323126
---

diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp
index 910e88c..de1a3b4 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.cpp
+++ b/llvm/lib/Target/X86/X86InstrInfo.cpp
@@ -8336,7 +8336,7 @@ void X86InstrInfo::breakPartialRegDependency(
     // Using XOR32rr because it has shorter encoding and zeros up the upper bits
     // as well.
     unsigned XReg = TRI->getSubReg(Reg, X86::sub_32bit);
-    BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(X86::XOR32rr), Reg)
+    BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(X86::XOR32rr), XReg)
         .addReg(XReg, RegState::Undef)
         .addReg(XReg, RegState::Undef)
         .addReg(Reg, RegState::ImplicitDefine);