From: Rui Salvaterra Date: Thu, 28 Apr 2022 22:57:55 +0000 (+0100) Subject: arm64: dts: mt7622: specify the L2 cache topology X-Git-Tag: v6.6.17~7444^2^2~5 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=80dd27b6c68c7189b865b4b966aa12c77d1adc1e;p=platform%2Fkernel%2Flinux-rpi.git arm64: dts: mt7622: specify the L2 cache topology On an MT7622 system, the kernel complains of not being able to detect the cache hierarchy of CPU 0. Specify the shared L2 cache node in the device tree, in order to fix this. Signed-off-by: Rui Salvaterra Link: https://lore.kernel.org/r/20220428225755.785153-1-rsalvaterra@gmail.com Signed-off-by: Matthias Brugger --- diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi index da1f88d..5551f00 100644 --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi @@ -80,6 +80,7 @@ enable-method = "psci"; clock-frequency = <1300000000>; cci-control-port = <&cci_control2>; + next-level-cache = <&L2>; }; cpu1: cpu@1 { @@ -94,6 +95,12 @@ enable-method = "psci"; clock-frequency = <1300000000>; cci-control-port = <&cci_control2>; + next-level-cache = <&L2>; + }; + + L2: l2-cache { + compatible = "cache"; + cache-level = <2>; }; };