From: Eric Anholt <eric@anholt.net>
Date: Mon, 18 Apr 2016 21:03:39 +0000 (-0700)
Subject: vc4: Fix fbo-generatemipmap-formats for NPOT.
X-Git-Tag: upstream/17.1.0~10963
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=802b9292aae724b8ac210fdb43681b05697a76bf;p=platform%2Fupstream%2Fmesa.git

vc4: Fix fbo-generatemipmap-formats for NPOT.

Single-sampled texture miplevels > 1 are stored in POT-aligned areas, but
we only get one value to control the stride of the src and dst for single
sampled buffers.  A RCL tile blit from level != 1 to level == 0 would
therefore load from the wrong stride.
---

diff --git a/src/gallium/drivers/vc4/vc4_blit.c b/src/gallium/drivers/vc4/vc4_blit.c
index 876c296..128a3e5 100644
--- a/src/gallium/drivers/vc4/vc4_blit.c
+++ b/src/gallium/drivers/vc4/vc4_blit.c
@@ -88,6 +88,26 @@ vc4_tile_blit(struct pipe_context *pctx, const struct pipe_blit_info *info)
                 return false;
         }
 
+        /* VC4_PACKET_LOAD_TILE_BUFFER_GENERAL uses the
+         * VC4_PACKET_TILE_RENDERING_MODE_CONFIG's width (determined by our
+         * destination surface) to determine the stride.  This may be wrong
+         * when reading from texture miplevels > 0, which are stored in
+         * POT-sized areas.  For MSAA, the tile addresses are computed
+         * explicitly by the RCL.
+         */
+        if (info->src.resource->nr_samples <= 1) {
+                struct vc4_resource *rsc = vc4_resource(info->src.resource);
+
+                uint32_t stride = dst_surface_width * rsc->cpp;
+                if (rsc->slices[info->src.level].tiling == VC4_TILING_FORMAT_T)
+                        stride = align(stride, 128);
+                else
+                        stride = align(stride, 16);
+
+                if (stride != rsc->slices[info->src.level].stride)
+                        return false;
+        }
+
         if (info->dst.resource->format != info->src.resource->format)
                 return false;