From: Ash Charles Date: Wed, 24 Jul 2013 19:22:35 +0000 (-0700) Subject: omap: overo: Use 200MHz SDRC timings for revision 1, 2 & 3 boards X-Git-Tag: v2013.10-rc1~22^2~22 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=802b3c7c1826018530acc8a7b8fe83f11614c937;p=platform%2Fkernel%2Fu-boot.git omap: overo: Use 200MHz SDRC timings for revision 1, 2 & 3 boards Gumstix uses 200Mhz RAM on revision 1, 2 & 3 COMs, so use 200MHz timings rather than 165MHz. Based on 6cf8bf44b1f8550e12f7f2a16e01890e5de8443d Signed-off-by: Ash Charles --- diff --git a/board/overo/overo.c b/board/overo/overo.c index 92d3de4..aace42a 100644 --- a/board/overo/overo.c +++ b/board/overo/overo.c @@ -142,16 +142,16 @@ void get_board_mem_timings(struct board_sdrc_timings *timings) timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; break; case REVISION_1: /* Micron 256MB/512MB, 1/2 banks of 256MB */ - timings->mcfg = MICRON_V_MCFG_165(256 << 20); - timings->ctrla = MICRON_V_ACTIMA_165; - timings->ctrlb = MICRON_V_ACTIMB_165; - timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + timings->mcfg = MICRON_V_MCFG_200(256 << 20); + timings->ctrla = MICRON_V_ACTIMA_200; + timings->ctrlb = MICRON_V_ACTIMB_200; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; break; case REVISION_2: /* Hynix 256MB/512MB, 1/2 banks of 256MB */ - timings->mcfg = HYNIX_V_MCFG_165(256 << 20); - timings->ctrla = HYNIX_V_ACTIMA_165; - timings->ctrlb = HYNIX_V_ACTIMB_165; - timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + timings->mcfg = HYNIX_V_MCFG_200(256 << 20); + timings->ctrla = HYNIX_V_ACTIMA_200; + timings->ctrlb = HYNIX_V_ACTIMB_200; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; break; case REVISION_3: /* Micron 512MB/1024MB, 1/2 banks of 512MB */ timings->mcfg = MCFG(512 << 20, 15);