From: Eric Anholt <eric@anholt.net>
Date: Tue, 16 Mar 2010 19:59:59 +0000 (-0700)
Subject: intel: Remove more code for x8z24 visuals, since we only do s8z24.
X-Git-Tag: 062012170305~14052
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=800a4b202f8b23540dbb128e780ca8b7e90d1f46;p=profile%2Fivi%2Fmesa.git

intel: Remove more code for x8z24 visuals, since we only do s8z24.
---

diff --git a/src/mesa/drivers/dri/intel/intel_screen.c b/src/mesa/drivers/dri/intel/intel_screen.c
index 6e4bb64..5e3f408 100644
--- a/src/mesa/drivers/dri/intel/intel_screen.c
+++ b/src/mesa/drivers/dri/intel/intel_screen.c
@@ -312,18 +312,13 @@ intelCreateBuffer(__DRIscreen * driScrnPriv,
       }
 
       if (mesaVis->depthBits == 24) {
-	 if (mesaVis->stencilBits == 8) {
-	    /* combined depth/stencil buffer */
-	    struct intel_renderbuffer *depthStencilRb
-	       = intel_create_renderbuffer(MESA_FORMAT_S8_Z24);
-	    /* note: bind RB to two attachment points */
-	    _mesa_add_renderbuffer(fb, BUFFER_DEPTH, &depthStencilRb->Base);
-	    _mesa_add_renderbuffer(fb, BUFFER_STENCIL, &depthStencilRb->Base);
-	 } else {
-	    struct intel_renderbuffer *depthRb
-	       = intel_create_renderbuffer(MESA_FORMAT_X8_Z24);
-	    _mesa_add_renderbuffer(fb, BUFFER_DEPTH, &depthRb->Base);
-	 }
+	 assert(mesaVis->stencilBits == 8);
+	 /* combined depth/stencil buffer */
+	 struct intel_renderbuffer *depthStencilRb
+	    = intel_create_renderbuffer(MESA_FORMAT_S8_Z24);
+	 /* note: bind RB to two attachment points */
+	 _mesa_add_renderbuffer(fb, BUFFER_DEPTH, &depthStencilRb->Base);
+	 _mesa_add_renderbuffer(fb, BUFFER_STENCIL, &depthStencilRb->Base);
       }
       else if (mesaVis->depthBits == 16) {
          /* just 16-bit depth buffer, no hw stencil */