From: Eric Anholt Date: Thu, 22 Sep 2011 18:58:37 +0000 (-0700) Subject: intel: Rename region->buffer to region->bo, and remove accessor function. X-Git-Tag: 062012170305~4205 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=8004a1cb95b8a195f3f4bbaa8d39d2f3297167de;p=profile%2Fivi%2Fmesa.git intel: Rename region->buffer to region->bo, and remove accessor function. We call all the other drm_intel_bo pointers in intel/*.h "bo", so this one was rather out of place. Acked-by: Kenneth Graunke --- diff --git a/src/mesa/drivers/dri/i915/i830_texstate.c b/src/mesa/drivers/dri/i915/i830_texstate.c index 71ce44f..7fb4c70 100644 --- a/src/mesa/drivers/dri/i915/i830_texstate.c +++ b/src/mesa/drivers/dri/i915/i830_texstate.c @@ -148,8 +148,8 @@ i830_update_tex_unit(struct intel_context *intel, GLuint unit, GLuint ss3) intel_miptree_get_image_offset(intelObj->mt, tObj->BaseLevel, 0, 0, &dst_x, &dst_y); - drm_intel_bo_reference(intelObj->mt->region->buffer); - i830->state.tex_buffer[unit] = intelObj->mt->region->buffer; + drm_intel_bo_reference(intelObj->mt->region->bo); + i830->state.tex_buffer[unit] = intelObj->mt->region->bo; pitch = intelObj->mt->region->pitch * intelObj->mt->cpp; /* XXX: This calculation is probably broken for tiled images with diff --git a/src/mesa/drivers/dri/i915/i830_vtbl.c b/src/mesa/drivers/dri/i915/i830_vtbl.c index ed5286f..7810f56 100644 --- a/src/mesa/drivers/dri/i915/i830_vtbl.c +++ b/src/mesa/drivers/dri/i915/i830_vtbl.c @@ -443,9 +443,9 @@ i830_emit_state(struct intel_context *intel) aper_array[aper_count++] = intel->batch.bo; if (dirty & I830_UPLOAD_BUFFERS) { - aper_array[aper_count++] = state->draw_region->buffer; + aper_array[aper_count++] = state->draw_region->bo; if (state->depth_region) - aper_array[aper_count++] = state->depth_region->buffer; + aper_array[aper_count++] = state->depth_region->bo; } for (i = 0; i < I830_TEX_UNITS; i++) @@ -501,13 +501,13 @@ i830_emit_state(struct intel_context *intel) BEGIN_BATCH(count); OUT_BATCH(state->Buffer[I830_DESTREG_CBUFADDR0]); OUT_BATCH(state->Buffer[I830_DESTREG_CBUFADDR1]); - OUT_RELOC(state->draw_region->buffer, + OUT_RELOC(state->draw_region->bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0); if (state->depth_region) { OUT_BATCH(state->Buffer[I830_DESTREG_DBUFADDR0]); OUT_BATCH(state->Buffer[I830_DESTREG_DBUFADDR1]); - OUT_RELOC(state->depth_region->buffer, + OUT_RELOC(state->depth_region->bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0); } diff --git a/src/mesa/drivers/dri/i915/i915_texstate.c b/src/mesa/drivers/dri/i915/i915_texstate.c index 5e789c4..cd2fb31 100644 --- a/src/mesa/drivers/dri/i915/i915_texstate.c +++ b/src/mesa/drivers/dri/i915/i915_texstate.c @@ -163,8 +163,8 @@ i915_update_tex_unit(struct intel_context *intel, GLuint unit, GLuint ss3) */ firstImage = tObj->Image[0][tObj->BaseLevel]; - drm_intel_bo_reference(intelObj->mt->region->buffer); - i915->state.tex_buffer[unit] = intelObj->mt->region->buffer; + drm_intel_bo_reference(intelObj->mt->region->bo); + i915->state.tex_buffer[unit] = intelObj->mt->region->bo; i915->state.tex_offset[unit] = 0; /* Always the origin of the miptree */ format = translate_texture_format(firstImage->TexFormat, diff --git a/src/mesa/drivers/dri/i915/i915_vtbl.c b/src/mesa/drivers/dri/i915/i915_vtbl.c index 495426a..1e84c6d 100644 --- a/src/mesa/drivers/dri/i915/i915_vtbl.c +++ b/src/mesa/drivers/dri/i915/i915_vtbl.c @@ -319,9 +319,9 @@ i915_emit_state(struct intel_context *intel) aper_array[aper_count++] = intel->batch.bo; if (dirty & I915_UPLOAD_BUFFERS) { if (state->draw_region) - aper_array[aper_count++] = state->draw_region->buffer; + aper_array[aper_count++] = state->draw_region->bo; if (state->depth_region) - aper_array[aper_count++] = state->depth_region->buffer; + aper_array[aper_count++] = state->depth_region->bo; } if (dirty & I915_UPLOAD_TEX_ALL) { @@ -397,7 +397,7 @@ i915_emit_state(struct intel_context *intel) OUT_BATCH(state->Buffer[I915_DESTREG_CBUFADDR0]); OUT_BATCH(state->Buffer[I915_DESTREG_CBUFADDR1]); if (state->draw_region) { - OUT_RELOC(state->draw_region->buffer, + OUT_RELOC(state->draw_region->bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0); } else { OUT_BATCH(0); @@ -406,7 +406,7 @@ i915_emit_state(struct intel_context *intel) OUT_BATCH(state->Buffer[I915_DESTREG_DBUFADDR0]); OUT_BATCH(state->Buffer[I915_DESTREG_DBUFADDR1]); if (state->depth_region) { - OUT_RELOC(state->depth_region->buffer, + OUT_RELOC(state->depth_region->bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0); } else { OUT_BATCH(0); diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c index 7b83ff5..2e6780b 100644 --- a/src/mesa/drivers/dri/i965/brw_misc_state.c +++ b/src/mesa/drivers/dri/i965/brw_misc_state.c @@ -205,11 +205,11 @@ static void prepare_depthbuffer(struct brw_context *brw) struct intel_renderbuffer *srb = intel_get_renderbuffer(fb, BUFFER_STENCIL); if (drb) - brw_add_validated_bo(brw, drb->region->buffer); + brw_add_validated_bo(brw, drb->region->bo); if (drb && drb->hiz_region) - brw_add_validated_bo(brw, drb->hiz_region->buffer); + brw_add_validated_bo(brw, drb->hiz_region->bo); if (srb) - brw_add_validated_bo(brw, srb->region->buffer); + brw_add_validated_bo(brw, srb->region->bo); } static void emit_depthbuffer(struct brw_context *brw) @@ -348,7 +348,7 @@ static void emit_depthbuffer(struct brw_context *brw) (BRW_TILEWALK_YMAJOR << 26) | ((region->tiling != I915_TILING_NONE) << 27) | (BRW_SURFACE_2D << 29)); - OUT_RELOC(region->buffer, + OUT_RELOC(region->bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, offset); OUT_BATCH((BRW_SURFACE_MIPMAPLAYOUT_BELOW << 1) | @@ -381,7 +381,7 @@ static void emit_depthbuffer(struct brw_context *brw) BEGIN_BATCH(3); OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2)); OUT_BATCH(hiz_region->pitch * hiz_region->cpp - 1); - OUT_RELOC(hiz_region->buffer, + OUT_RELOC(hiz_region->bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0); ADVANCE_BATCH(); @@ -398,7 +398,7 @@ static void emit_depthbuffer(struct brw_context *brw) BEGIN_BATCH(3); OUT_BATCH((_3DSTATE_STENCIL_BUFFER << 16) | (3 - 2)); OUT_BATCH(stencil_irb->region->pitch * stencil_irb->region->cpp - 1); - OUT_RELOC(stencil_irb->region->buffer, + OUT_RELOC(stencil_irb->region->bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0); ADVANCE_BATCH(); diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c index 5be5c16..aae1eed 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c @@ -244,7 +244,7 @@ brw_update_texture_surface( struct gl_context *ctx, GLuint unit ) sampler->sRGBDecode) << BRW_SURFACE_FORMAT_SHIFT)); - surf[1] = intelObj->mt->region->buffer->offset; /* reloc */ + surf[1] = intelObj->mt->region->bo->offset; /* reloc */ surf[2] = ((intelObj->_MaxLevel - tObj->BaseLevel) << BRW_SURFACE_LOD_SHIFT | (firstImage->Width - 1) << BRW_SURFACE_WIDTH_SHIFT | @@ -261,7 +261,7 @@ brw_update_texture_surface( struct gl_context *ctx, GLuint unit ) /* Emit relocation to surface contents */ drm_intel_bo_emit_reloc(brw->intel.batch.bo, brw->wm.surf_offset[surf_index] + 4, - intelObj->mt->region->buffer, 0, + intelObj->mt->region->bo, 0, I915_GEM_DOMAIN_SAMPLER, 0); } @@ -488,7 +488,7 @@ brw_update_renderbuffer_surface(struct brw_context *brw, /* reloc */ surf[1] = (intel_renderbuffer_tile_offsets(irb, &tile_x, &tile_y) + - region->buffer->offset); + region->bo->offset); surf[2] = ((rb->Width - 1) << BRW_SURFACE_WIDTH_SHIFT | (rb->Height - 1) << BRW_SURFACE_HEIGHT_SHIFT); @@ -531,8 +531,8 @@ brw_update_renderbuffer_surface(struct brw_context *brw, drm_intel_bo_emit_reloc(brw->intel.batch.bo, brw->wm.surf_offset[unit] + 4, - region->buffer, - surf[1] - region->buffer->offset, + region->bo, + surf[1] - region->bo->offset, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER); } @@ -550,7 +550,7 @@ prepare_wm_surfaces(struct brw_context *brw) struct intel_region *region = irb ? irb->region : NULL; if (region) - brw_add_validated_bo(brw, region->buffer); + brw_add_validated_bo(brw, region->bo); nr_surfaces = SURF_INDEX_DRAW(i) + 1; } @@ -566,7 +566,7 @@ prepare_wm_surfaces(struct brw_context *brw) struct gl_texture_object *tObj = texUnit->_Current; struct intel_texture_object *intelObj = intel_texture_object(tObj); - brw_add_validated_bo(brw, intelObj->mt->region->buffer); + brw_add_validated_bo(brw, intelObj->mt->region->bo); nr_surfaces = SURF_INDEX_TEXTURE(i) + 1; } } diff --git a/src/mesa/drivers/dri/i965/gen7_misc_state.c b/src/mesa/drivers/dri/i965/gen7_misc_state.c index 9eb75e2..e160641 100644 --- a/src/mesa/drivers/dri/i965/gen7_misc_state.c +++ b/src/mesa/drivers/dri/i965/gen7_misc_state.c @@ -65,9 +65,9 @@ static void prepare_depthbuffer(struct brw_context *brw) struct intel_renderbuffer *srb = intel_get_renderbuffer(fb, BUFFER_STENCIL); if (drb) - brw_add_validated_bo(brw, drb->region->buffer); + brw_add_validated_bo(brw, drb->region->bo); if (srb) - brw_add_validated_bo(brw, srb->region->buffer); + brw_add_validated_bo(brw, srb->region->bo); } static void emit_depthbuffer(struct brw_context *brw) @@ -128,7 +128,7 @@ static void emit_depthbuffer(struct brw_context *brw) ((srb != NULL && ctx->Stencil.WriteMask != 0) << 27) | ((ctx->Depth.Mask != 0) << 28) | (BRW_SURFACE_2D << 29)); - OUT_RELOC(region->buffer, + OUT_RELOC(region->bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, offset); OUT_BATCH(((region->width - 1) << 4) | ((region->height - 1) << 18)); @@ -155,7 +155,7 @@ static void emit_depthbuffer(struct brw_context *brw) BEGIN_BATCH(3); OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER << 16 | (3 - 2)); OUT_BATCH(srb->region->pitch * srb->region->cpp - 1); - OUT_RELOC(srb->region->buffer, + OUT_RELOC(srb->region->bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0); ADVANCE_BATCH(); diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c index 4add1a6..b148c53 100644 --- a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c @@ -95,7 +95,7 @@ gen7_update_texture_surface(struct gl_context *ctx, GLuint unit) * - render_cache_read_write (exists on gen6 but ignored here) */ - surf->ss1.base_addr = intelObj->mt->region->buffer->offset; /* reloc */ + surf->ss1.base_addr = intelObj->mt->region->bo->offset; /* reloc */ surf->ss2.width = firstImage->Width - 1; surf->ss2.height = firstImage->Height - 1; @@ -118,7 +118,7 @@ gen7_update_texture_surface(struct gl_context *ctx, GLuint unit) drm_intel_bo_emit_reloc(brw->intel.batch.bo, brw->wm.surf_offset[surf_index] + offsetof(struct gen7_surface_state, ss1), - intelObj->mt->region->buffer, 0, + intelObj->mt->region->bo, 0, I915_GEM_DOMAIN_SAMPLER, 0); } @@ -275,7 +275,7 @@ gen7_update_renderbuffer_surface(struct brw_context *brw, surf->ss0.surface_type = BRW_SURFACE_2D; /* reloc */ surf->ss1.base_addr = intel_renderbuffer_tile_offsets(irb, &tile_x, &tile_y); - surf->ss1.base_addr += region->buffer->offset; /* reloc */ + surf->ss1.base_addr += region->bo->offset; /* reloc */ assert(brw->has_surface_tile_offset); /* Note that the low bits of these fields are missing, so @@ -294,8 +294,8 @@ gen7_update_renderbuffer_surface(struct brw_context *brw, drm_intel_bo_emit_reloc(brw->intel.batch.bo, brw->wm.surf_offset[unit] + offsetof(struct gen7_surface_state, ss1), - region->buffer, - surf->ss1.base_addr - region->buffer->offset, + region->bo, + surf->ss1.base_addr - region->bo->offset, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER); } @@ -314,7 +314,7 @@ prepare_wm_surfaces(struct brw_context *brw) struct intel_region *region = irb ? irb->region : NULL; if (region) - brw_add_validated_bo(brw, region->buffer); + brw_add_validated_bo(brw, region->bo); nr_surfaces = SURF_INDEX_DRAW(i) + 1; } } @@ -330,7 +330,7 @@ prepare_wm_surfaces(struct brw_context *brw) struct intel_texture_object *intelObj = intel_texture_object(tObj); if (texUnit->_ReallyEnabled) { - brw_add_validated_bo(brw, intelObj->mt->region->buffer); + brw_add_validated_bo(brw, intelObj->mt->region->bo); nr_surfaces = SURF_INDEX_TEXTURE(i) + 1; } } diff --git a/src/mesa/drivers/dri/intel/intel_blit.c b/src/mesa/drivers/dri/intel/intel_blit.c index 5a86648..f0401b7 100644 --- a/src/mesa/drivers/dri/intel/intel_blit.c +++ b/src/mesa/drivers/dri/intel/intel_blit.c @@ -223,7 +223,6 @@ intelClearWithBlit(struct gl_context *ctx, GLbitfield mask) struct intel_context *intel = intel_context(ctx); struct gl_framebuffer *fb = ctx->DrawBuffer; GLuint clear_depth_value, clear_depth_mask; - GLboolean all; GLint cx, cy, cw, ch; GLbitfield fail_mask = 0; BATCH_LOCALS; @@ -253,15 +252,12 @@ intelClearWithBlit(struct gl_context *ctx, GLbitfield mask) if (cw == 0 || ch == 0) return 0; - all = (cw == fb->Width && ch == fb->Height); - /* Loop over all renderbuffers */ mask &= (1 << BUFFER_COUNT) - 1; while (mask) { GLuint buf = _mesa_ffs(mask) - 1; GLboolean is_depth_stencil = buf == BUFFER_DEPTH || buf == BUFFER_STENCIL; struct intel_renderbuffer *irb; - drm_intel_bo *write_buffer; int x1, y1, x2, y2; uint32_t clear_val; uint32_t BR13, CMD; @@ -271,15 +267,12 @@ intelClearWithBlit(struct gl_context *ctx, GLbitfield mask) mask &= ~(1 << buf); irb = intel_get_renderbuffer(fb, buf); - if (irb == NULL || irb->region == NULL || irb->region->buffer == NULL) { + if (irb == NULL || irb->region == NULL || irb->region->bo == NULL) { fail_mask |= 1 << buf; continue; } /* OK, clear this renderbuffer */ - write_buffer = intel_region_buffer(intel, irb->region, - all ? INTEL_WRITE_FULL : - INTEL_WRITE_PART); x1 = cx + irb->draw_x; y1 = cy + irb->draw_y; x2 = cx + cw + irb->draw_x; @@ -290,7 +283,7 @@ intelClearWithBlit(struct gl_context *ctx, GLbitfield mask) DBG("%s dst:buf(%p)/%d %d,%d sz:%dx%d\n", __FUNCTION__, - irb->region->buffer, (pitch * cpp), + irb->region->bo, (pitch * cpp), x1, y1, x2 - x1, y2 - y1); BR13 = 0xf0 << 16; @@ -358,7 +351,7 @@ intelClearWithBlit(struct gl_context *ctx, GLbitfield mask) /* do space check before going any further */ aper_array[0] = intel->batch.bo; - aper_array[1] = write_buffer; + aper_array[1] = irb->region->bo; if (drm_intel_bufmgr_check_aperture_space(aper_array, ARRAY_SIZE(aper_array)) != 0) { @@ -370,7 +363,7 @@ intelClearWithBlit(struct gl_context *ctx, GLbitfield mask) OUT_BATCH(BR13); OUT_BATCH((y1 << 16) | x1); OUT_BATCH((y2 << 16) | x2); - OUT_RELOC_FENCED(write_buffer, + OUT_RELOC_FENCED(irb->region->bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0); OUT_BATCH(clear_val); @@ -553,7 +546,7 @@ intel_set_teximage_alpha_to_one(struct gl_context *ctx, DBG("%s dst:buf(%p)/%d %d,%d sz:%dx%d\n", __FUNCTION__, - intel_image->mt->region->buffer, (pitch * cpp), + intel_image->mt->region->bo, (pitch * cpp), x1, y1, x2 - x1, y2 - y1); BR13 = br13_for_cpp(cpp) | 0xf0 << 16; @@ -572,7 +565,7 @@ intel_set_teximage_alpha_to_one(struct gl_context *ctx, /* do space check before going any further */ aper_array[0] = intel->batch.bo; - aper_array[1] = region->buffer; + aper_array[1] = region->bo; if (drm_intel_bufmgr_check_aperture_space(aper_array, ARRAY_SIZE(aper_array)) != 0) { @@ -584,7 +577,7 @@ intel_set_teximage_alpha_to_one(struct gl_context *ctx, OUT_BATCH(BR13); OUT_BATCH((y1 << 16) | x1); OUT_BATCH((y2 << 16) | x2); - OUT_RELOC_FENCED(region->buffer, + OUT_RELOC_FENCED(region->bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0); OUT_BATCH(0xffffffff); /* white, but only alpha gets written */ diff --git a/src/mesa/drivers/dri/intel/intel_buffer_objects.c b/src/mesa/drivers/dri/intel/intel_buffer_objects.c index 4df2d76..c52afbd 100644 --- a/src/mesa/drivers/dri/intel/intel_buffer_objects.c +++ b/src/mesa/drivers/dri/intel/intel_buffer_objects.c @@ -752,7 +752,7 @@ intel_texture_object_purgeable(struct gl_context * ctx, if (intel->mt == NULL || intel->mt->region == NULL) return GL_RELEASED_APPLE; - return intel_buffer_purgeable(intel->mt->region->buffer); + return intel_buffer_purgeable(intel->mt->region->bo); } static GLenum @@ -769,7 +769,7 @@ intel_render_object_purgeable(struct gl_context * ctx, if (intel->region == NULL) return GL_RELEASED_APPLE; - return intel_buffer_purgeable(intel->region->buffer); + return intel_buffer_purgeable(intel->region->bo); } static GLenum @@ -809,7 +809,7 @@ intel_texture_object_unpurgeable(struct gl_context * ctx, if (intel->mt == NULL || intel->mt->region == NULL) return GL_UNDEFINED_APPLE; - return intel_buffer_unpurgeable(intel->mt->region->buffer); + return intel_buffer_unpurgeable(intel->mt->region->bo); } static GLenum @@ -826,7 +826,7 @@ intel_render_object_unpurgeable(struct gl_context * ctx, if (intel->region == NULL) return GL_UNDEFINED_APPLE; - return intel_buffer_unpurgeable(intel->region->buffer); + return intel_buffer_unpurgeable(intel->region->bo); } #endif diff --git a/src/mesa/drivers/dri/intel/intel_pixel_bitmap.c b/src/mesa/drivers/dri/intel/intel_pixel_bitmap.c index d9873a3..e2d0eda 100644 --- a/src/mesa/drivers/dri/intel/intel_pixel_bitmap.c +++ b/src/mesa/drivers/dri/intel/intel_pixel_bitmap.c @@ -274,7 +274,7 @@ do_blit_bitmap( struct gl_context *ctx, sz, color, dst->pitch, - dst->buffer, + dst->bo, 0, dst->tiling, dstx + px, diff --git a/src/mesa/drivers/dri/intel/intel_pixel_read.c b/src/mesa/drivers/dri/intel/intel_pixel_read.c index b2e77c7..c8e415d 100644 --- a/src/mesa/drivers/dri/intel/intel_pixel_read.c +++ b/src/mesa/drivers/dri/intel/intel_pixel_read.c @@ -149,7 +149,7 @@ do_blit_readpixels(struct gl_context * ctx, if (!intelEmitCopyBlit(intel, src->cpp, - src->pitch, src->buffer, 0, src->tiling, + src->pitch, src->bo, 0, src->tiling, rowLength, dst_buffer, dst_offset, GL_FALSE, x, y, dst_x, dst_y, diff --git a/src/mesa/drivers/dri/intel/intel_regions.c b/src/mesa/drivers/dri/intel/intel_regions.c index 4d4ddd9..9cb1632 100644 --- a/src/mesa/drivers/dri/intel/intel_regions.c +++ b/src/mesa/drivers/dri/intel/intel_regions.c @@ -116,10 +116,10 @@ intel_region_map(struct intel_context *intel, struct intel_region *region) _DBG("%s %p\n", __FUNCTION__, region); if (!region->map_refcount++) { if (region->tiling != I915_TILING_NONE) - drm_intel_gem_bo_map_gtt(region->buffer); + drm_intel_gem_bo_map_gtt(region->bo); else - drm_intel_bo_map(region->buffer, GL_TRUE); - region->map = region->buffer->virtual; + drm_intel_bo_map(region->bo, GL_TRUE); + region->map = region->bo->virtual; } return region->map; @@ -131,9 +131,9 @@ intel_region_unmap(struct intel_context *intel, struct intel_region *region) _DBG("%s %p\n", __FUNCTION__, region); if (!--region->map_refcount) { if (region->tiling != I915_TILING_NONE) - drm_intel_gem_bo_unmap_gtt(region->buffer); + drm_intel_gem_bo_unmap_gtt(region->bo); else - drm_intel_bo_unmap(region->buffer); + drm_intel_bo_unmap(region->bo); region->map = NULL; } } @@ -155,7 +155,7 @@ intel_region_alloc_internal(struct intel_screen *screen, region->height = height; region->pitch = pitch; region->refcount = 1; - region->buffer = buffer; + region->bo = buffer; region->tiling = tiling; region->screen = screen; @@ -197,7 +197,7 @@ GLboolean intel_region_flink(struct intel_region *region, uint32_t *name) { if (region->name == 0) { - if (drm_intel_bo_flink(region->buffer, ®ion->name)) + if (drm_intel_bo_flink(region->bo, ®ion->name)) return GL_FALSE; _mesa_HashInsert(region->screen->named_regions, @@ -292,7 +292,7 @@ intel_region_release(struct intel_region **region_handle) if (region->refcount == 0) { assert(region->map_refcount == 0); - drm_intel_bo_unreference(region->buffer); + drm_intel_bo_unreference(region->bo); if (region->name > 0) _mesa_HashRemove(region->screen->named_regions, region->name); @@ -396,15 +396,8 @@ intel_region_copy(struct intel_context *intel, return intelEmitCopyBlit(intel, dst->cpp, - src_pitch, src->buffer, src_offset, src->tiling, - dst->pitch, dst->buffer, dst_offset, dst->tiling, + src_pitch, src->bo, src_offset, src->tiling, + dst->pitch, dst->bo, dst_offset, dst->tiling, srcx, srcy, dstx, dsty, width, height, logicop); } - -drm_intel_bo * -intel_region_buffer(struct intel_context *intel, - struct intel_region *region, GLuint flag) -{ - return region->buffer; -} diff --git a/src/mesa/drivers/dri/intel/intel_regions.h b/src/mesa/drivers/dri/intel/intel_regions.h index f3f6a07..61a284a 100644 --- a/src/mesa/drivers/dri/intel/intel_regions.h +++ b/src/mesa/drivers/dri/intel/intel_regions.h @@ -53,7 +53,7 @@ struct intel_buffer_object; */ struct intel_region { - drm_intel_bo *buffer; /**< buffer manager's buffer */ + drm_intel_bo *bo; /**< buffer manager's buffer */ GLuint refcount; /**< Reference count for region */ GLuint cpp; /**< bytes per pixel */ GLuint width; /**< in pixels */ @@ -124,10 +124,6 @@ intel_region_copy(struct intel_context *intel, GLboolean flip, GLenum logicop); -drm_intel_bo *intel_region_buffer(struct intel_context *intel, - struct intel_region *region, - GLuint flag); - void _mesa_copy_rect(GLubyte * dst, GLuint cpp, GLuint dst_pitch, diff --git a/src/mesa/drivers/dri/intel/intel_screen.c b/src/mesa/drivers/dri/intel/intel_screen.c index 2909486..777f53a 100644 --- a/src/mesa/drivers/dri/intel/intel_screen.c +++ b/src/mesa/drivers/dri/intel/intel_screen.c @@ -283,7 +283,7 @@ intel_query_image(__DRIimage *image, int attrib, int *value) *value = image->region->pitch * image->region->cpp; return GL_TRUE; case __DRI_IMAGE_ATTRIB_HANDLE: - *value = image->region->buffer->handle; + *value = image->region->bo->handle; return GL_TRUE; case __DRI_IMAGE_ATTRIB_NAME: return intel_region_flink(image->region, (uint32_t *) value); diff --git a/src/mesa/drivers/dri/intel/intel_span.c b/src/mesa/drivers/dri/intel/intel_span.c index 2e1c80c..8da3b11 100644 --- a/src/mesa/drivers/dri/intel/intel_span.c +++ b/src/mesa/drivers/dri/intel/intel_span.c @@ -139,7 +139,7 @@ intel_set_span_functions(struct intel_context *intel, * required. \ */ \ struct intel_renderbuffer *irb = intel_renderbuffer(rb); \ - uint8_t *buf = irb->region->buffer->virtual; \ + uint8_t *buf = irb->region->bo->virtual; \ unsigned stride = irb->region->pitch; \ unsigned height = 2 * irb->region->height; \ bool flip = rb->Name == 0; \ @@ -234,9 +234,9 @@ intel_renderbuffer_map(struct intel_context *intel, struct gl_renderbuffer *rb) if (!irb->region) return; - drm_intel_gem_bo_map_gtt(irb->region->buffer); + drm_intel_gem_bo_map_gtt(irb->region->bo); - rb->Data = irb->region->buffer->virtual; + rb->Data = irb->region->bo->virtual; rb->RowStride = irb->region->pitch; if (!rb->Name) { @@ -271,7 +271,7 @@ intel_renderbuffer_unmap(struct intel_context *intel, if (!irb->region) return; - drm_intel_gem_bo_unmap_gtt(irb->region->buffer); + drm_intel_gem_bo_unmap_gtt(irb->region->bo); rb->GetRow = NULL; rb->PutRow = NULL; diff --git a/src/mesa/drivers/dri/intel/intel_tex_copy.c b/src/mesa/drivers/dri/intel/intel_tex_copy.c index 326f62f..907ce7f 100644 --- a/src/mesa/drivers/dri/intel/intel_tex_copy.c +++ b/src/mesa/drivers/dri/intel/intel_tex_copy.c @@ -109,9 +109,6 @@ intel_copy_texsubimage(struct intel_context *intel, } { - drm_intel_bo *dst_bo = intel_region_buffer(intel, - intelImage->mt->region, - INTEL_WRITE_PART); GLuint image_x, image_y; GLshort src_pitch; @@ -140,11 +137,11 @@ intel_copy_texsubimage(struct intel_context *intel, if (!intelEmitCopyBlit(intel, intelImage->mt->cpp, src_pitch, - irb->region->buffer, + irb->region->bo, 0, irb->region->tiling, intelImage->mt->region->pitch, - dst_bo, + intelImage->mt->region->bo, 0, intelImage->mt->region->tiling, irb->draw_x + x, irb->draw_y + y, diff --git a/src/mesa/drivers/dri/intel/intel_tex_image.c b/src/mesa/drivers/dri/intel/intel_tex_image.c index 060f22c..ecccb47 100644 --- a/src/mesa/drivers/dri/intel/intel_tex_image.c +++ b/src/mesa/drivers/dri/intel/intel_tex_image.c @@ -180,7 +180,7 @@ try_pbo_upload(struct intel_context *intel, return false; } - dst_buffer = intel_region_buffer(intel, intelImage->mt->region, INTEL_WRITE_FULL); + dst_buffer = intelImage->mt->region->bo; src_buffer = intel_bufferobj_source(intel, pbo, 64, &src_offset); /* note: potential 64-bit ptr to 32-bit int cast */ src_offset += (GLuint) (unsigned long) pixels; @@ -411,7 +411,7 @@ intelTexImage(struct gl_context * ctx, if (pixels != NULL) { /* Flush any queued rendering with the texture before mapping. */ if (drm_intel_bo_references(intel->batch.bo, - intelImage->mt->region->buffer)) { + intelImage->mt->region->bo)) { intel_flush(ctx); } texImage->Data = intel_miptree_image_map(intel, diff --git a/src/mesa/drivers/dri/intel/intel_tex_subimage.c b/src/mesa/drivers/dri/intel/intel_tex_subimage.c index 0da348c..e58d906 100644 --- a/src/mesa/drivers/dri/intel/intel_tex_subimage.c +++ b/src/mesa/drivers/dri/intel/intel_tex_subimage.c @@ -53,7 +53,7 @@ intel_blit_texsubimage(struct gl_context * ctx, struct intel_context *intel = intel_context(ctx); struct intel_texture_image *intelImage = intel_texture_image(texImage); GLuint dstRowStride = 0; - drm_intel_bo *temp_bo = NULL, *dst_bo = NULL; + drm_intel_bo *temp_bo = NULL; unsigned int blit_x = 0, blit_y = 0; unsigned long pitch; uint32_t tiling_mode = I915_TILING_NONE; @@ -77,10 +77,7 @@ intel_blit_texsubimage(struct gl_context * ctx, if (intel->gen >= 6) return false; - dst_bo = intel_region_buffer(intel, intelImage->mt->region, - INTEL_WRITE_PART); - - if (!drm_intel_bo_busy(dst_bo)) + if (!drm_intel_bo_busy(intelImage->mt->region->bo)) return false; DBG("BLT subimage %s target %s level %d offset %d,%d %dx%d\n", @@ -145,7 +142,8 @@ intel_blit_texsubimage(struct gl_context * ctx, intelImage->mt->cpp, dstRowStride / intelImage->mt->cpp, temp_bo, 0, GL_FALSE, - dst_pitch / intelImage->mt->cpp, dst_bo, 0, + dst_pitch / intelImage->mt->cpp, + intelImage->mt->region->bo, 0, intelImage->mt->region->tiling, 0, 0, blit_x, blit_y, width, height, GL_COPY);