From: Caio Marcelo de Oliveira Filho Date: Sat, 22 Jun 2019 07:25:48 +0000 (-0700) Subject: i965: Move resources lowering after NIR linking X-Git-Tag: upstream/19.3.0~5175 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=7fc907118e5756e2ab3911e670dad103f4095a19;p=platform%2Fupstream%2Fmesa.git i965: Move resources lowering after NIR linking Those either depend on information filled by the NIR linking steps OR are restricted by those: - gl_nir_lower_samplers: depends on UniformStorage being set by the linker. - brw_nir_lower_image_load_store: After 6981069fc80 "i965: Ignore uniform storage for samplers or images, use binding info" we want this pass to happen after gl_nir_lower_samplers. - gl_nir_lower_buffers: depends on UniformBlocks and SharedStorageBlocks being set by the linker. For the regular GLSL code path, those datastructures are filled earlier. For NIR linking code path we need to generate the nir_shader first then process it -- and currently the processing works with all shaders together. So move the passes out of brw_create_nir into its own function, called by the brwProgramStringNotify and brw_link_shader(). This patch prepares ground for ARB_gl_spirv, that will make use of NIR linker. Reviewed-by: Timothy Arceri Reviewed-by: Kenneth Graunke --- diff --git a/src/mesa/drivers/dri/i965/brw_link.cpp b/src/mesa/drivers/dri/i965/brw_link.cpp index 61d3173..8d718f3 100644 --- a/src/mesa/drivers/dri/i965/brw_link.cpp +++ b/src/mesa/drivers/dri/i965/brw_link.cpp @@ -261,6 +261,12 @@ brw_link_shader(struct gl_context *ctx, struct gl_shader_program *shProg) compiler->scalar_stage[stage]); } + /* TODO: Verify if its feasible to split up the NIR linking work into a + * per-stage part (that fill out information we need for the passes) and a + * actual linking part, so that we could fold back brw_nir_lower_resources + * back into brw_create_nir. + */ + /* SPIR-V programs use a NIR linker */ if (shProg->data->spirv) { if (!gl_nir_link_uniforms(ctx, shProg)) @@ -277,6 +283,8 @@ brw_link_shader(struct gl_context *ctx, struct gl_shader_program *shProg) struct gl_program *prog = shader->Program; + brw_nir_lower_resources(prog->nir, shProg, prog, &brw->screen->devinfo); + NIR_PASS_V(prog->nir, brw_nir_lower_gl_images, prog); } diff --git a/src/mesa/drivers/dri/i965/brw_program.c b/src/mesa/drivers/dri/i965/brw_program.c index 87d6bba..aa7961f 100644 --- a/src/mesa/drivers/dri/i965/brw_program.c +++ b/src/mesa/drivers/dri/i965/brw_program.c @@ -119,16 +119,6 @@ brw_create_nir(struct brw_context *brw, brw_preprocess_nir(brw->screen->compiler, nir, softfp64); - NIR_PASS_V(nir, gl_nir_lower_samplers, shader_prog); - prog->info.textures_used = nir->info.textures_used; - prog->info.textures_used_by_txf = nir->info.textures_used_by_txf; - - NIR_PASS_V(nir, brw_nir_lower_image_load_store, devinfo); - - NIR_PASS_V(nir, gl_nir_lower_buffers, shader_prog); - /* Do a round of constant folding to clean up address calculations */ - NIR_PASS_V(nir, nir_opt_constant_folding); - if (stage == MESA_SHADER_TESS_CTRL) { /* Lower gl_PatchVerticesIn from a sys. value to a uniform on Gen8+. */ static const gl_state_index16 tokens[STATE_LENGTH] = @@ -170,6 +160,22 @@ brw_create_nir(struct brw_context *brw, } void +brw_nir_lower_resources(nir_shader *nir, struct gl_shader_program *shader_prog, + struct gl_program *prog, + const struct gen_device_info *devinfo) +{ + NIR_PASS_V(prog->nir, gl_nir_lower_samplers, shader_prog); + prog->info.textures_used = prog->nir->info.textures_used; + prog->info.textures_used_by_txf = prog->nir->info.textures_used_by_txf; + + NIR_PASS_V(prog->nir, brw_nir_lower_image_load_store, devinfo); + + NIR_PASS_V(prog->nir, gl_nir_lower_buffers, shader_prog); + /* Do a round of constant folding to clean up address calculations */ + NIR_PASS_V(prog->nir, nir_opt_constant_folding); +} + +void brw_shader_gather_info(nir_shader *nir, struct gl_program *prog) { nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir)); @@ -262,6 +268,8 @@ brwProgramStringNotify(struct gl_context *ctx, prog->nir = brw_create_nir(brw, NULL, prog, MESA_SHADER_FRAGMENT, true); + brw_nir_lower_resources(prog->nir, NULL, prog, &brw->screen->devinfo); + brw_shader_gather_info(prog->nir, prog); brw_fs_precompile(ctx, prog); @@ -286,6 +294,8 @@ brwProgramStringNotify(struct gl_context *ctx, prog->nir = brw_create_nir(brw, NULL, prog, MESA_SHADER_VERTEX, compiler->scalar_stage[MESA_SHADER_VERTEX]); + brw_nir_lower_resources(prog->nir, NULL, prog, &brw->screen->devinfo); + brw_shader_gather_info(prog->nir, prog); brw_vs_precompile(ctx, prog); diff --git a/src/mesa/drivers/dri/i965/brw_program.h b/src/mesa/drivers/dri/i965/brw_program.h index 8eb9620..9227329 100644 --- a/src/mesa/drivers/dri/i965/brw_program.h +++ b/src/mesa/drivers/dri/i965/brw_program.h @@ -64,6 +64,11 @@ struct nir_shader *brw_create_nir(struct brw_context *brw, gl_shader_stage stage, bool is_scalar); +void brw_nir_lower_resources(nir_shader *nir, + struct gl_shader_program *shader_prog, + struct gl_program *prog, + const struct gen_device_info *devinfo); + void brw_shader_gather_info(nir_shader *nir, struct gl_program *prog); void brw_setup_tex_for_precompile(const struct gen_device_info *devinfo,