From: Kenneth Graunke <kenneth@whitecape.org>
Date: Fri, 13 May 2011 16:25:27 +0000 (-0700)
Subject: i965: Disable register spilling on Ivybridge for now.
X-Git-Tag: mesa-7.11-rc1~658
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=7f5e0d2a908d4f7ba781d70731172a07b640f401;p=platform%2Fupstream%2Fmesa.git

i965: Disable register spilling on Ivybridge for now.

The data port messages for this are rather different.  For now, fail to
compile rather than hanging the GPU.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
---

diff --git a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
index 1e2cf91..f88b131 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
@@ -244,6 +244,8 @@ fs_visitor::assign_regs()
 
       if (reg == -1) {
 	 fail("no register to spill\n");
+      } else if (intel->gen >= 7) {
+	 fail("no spilling support on gen7 yet\n");
       } else if (c->dispatch_width == 16) {
 	 fail("no spilling support on 16-wide yet\n");
       } else {