From: Craig Topper Date: Fri, 23 Mar 2018 06:41:38 +0000 (+0000) Subject: [X86] Merge VMOVMSKBrr and MOVMSKBrr in the SNB sheduler model. X-Git-Tag: llvmorg-7.0.0-rc1~9858 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=7f142b8bf1b73495bd53687a7ae2698e1106e3e3;p=platform%2Fupstream%2Fllvm.git [X86] Merge VMOVMSKBrr and MOVMSKBrr in the SNB sheduler model. The VMOVMSKBrr was in a separate InstRW with a lower latency, but I assume they should be the same and the higher latency matches Agners table so I'm going with that. llvm-svn: 328291 --- diff --git a/llvm/lib/Target/X86/X86SchedSandyBridge.td b/llvm/lib/Target/X86/X86SchedSandyBridge.td index 155aa743d69e..89d3a5f537bd 100644 --- a/llvm/lib/Target/X86/X86SchedSandyBridge.td +++ b/llvm/lib/Target/X86/X86SchedSandyBridge.td @@ -258,8 +258,7 @@ def SBWriteResGroup0 : SchedWriteRes<[SBPort0]> { let NumMicroOps = 1; let ResourceCycles = [1]; } -def: InstRW<[SBWriteResGroup0], (instregex "VPMOVMSKBrr", - "(V?)CVTSS2SDrr", +def: InstRW<[SBWriteResGroup0], (instregex "(V?)CVTSS2SDrr", "(V?)PSLLDri", "(V?)PSLLQri", "(V?)PSLLWri", @@ -551,7 +550,7 @@ def SBWriteResGroup7 : SchedWriteRes<[SBPort0]> { let NumMicroOps = 1; let ResourceCycles = [1]; } -def: InstRW<[SBWriteResGroup7], (instregex "PMOVMSKBrr", +def: InstRW<[SBWriteResGroup7], (instregex "(V?)PMOVMSKBrr", "VMOVMSKPDYrr", "(V?)MOVMSKPDrr", "VMOVMSKPSYrr", diff --git a/llvm/test/CodeGen/X86/sse2-schedule.ll b/llvm/test/CodeGen/X86/sse2-schedule.ll index 37edfa0f2d9d..f9d7c995e756 100644 --- a/llvm/test/CodeGen/X86/sse2-schedule.ll +++ b/llvm/test/CodeGen/X86/sse2-schedule.ll @@ -5987,7 +5987,7 @@ define i32 @test_pmovmskb(<16 x i8> %a0) { ; ; SANDY-LABEL: test_pmovmskb: ; SANDY: # %bb.0: -; SANDY-NEXT: vpmovmskb %xmm0, %eax # sched: [1:1.00] +; SANDY-NEXT: vpmovmskb %xmm0, %eax # sched: [2:1.00] ; SANDY-NEXT: retq # sched: [1:1.00] ; ; HASWELL-LABEL: test_pmovmskb: