From: Damien Le Moal Date: Wed, 10 Feb 2021 05:02:17 +0000 (+0900) Subject: dt-bindings: update risc-v cpu properties X-Git-Tag: accepted/tizen/unified/20230118.172025~7720^2~21 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=7ef71c719eb462edaa6078405654d2447c7a5488;p=platform%2Fkernel%2Flinux-rpi.git dt-bindings: update risc-v cpu properties The Canaan Kendryte K210 SoC CPU cores are based on a rocket chip version using a draft verion of the RISC-V ISA specifications. To avoid any confusion with CPU cores using stable specifications, add the compatible string "canaan,k210" for this SoC CPU cores. Also add the "riscv,none" value to the mmu-type property to allow a DT to indicate that the CPU being described does not have an MMU or that it has an MMU that is not usable (which is the case for the K210 SoC). Signed-off-by: Damien Le Moal Reviewed-by: Atish Patra Reviewed-by: Anup Patel Acked-by: Rob Herring Signed-off-by: Palmer Dabbelt --- diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index eb6843f..e534f6a 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -39,6 +39,7 @@ properties: - sifive,u74 - sifive,u5 - sifive,u7 + - canaan,k210 - const: riscv - const: riscv # Simulator only description: @@ -56,6 +57,7 @@ properties: - riscv,sv32 - riscv,sv39 - riscv,sv48 + - riscv,none riscv,isa: description: