From: Andreas Krebbel Date: Thu, 12 Nov 2020 07:20:43 +0000 (+0100) Subject: IBM Z: Rename mode attr tointvec to TOINTVEC X-Git-Tag: upstream/12.2.0~12020 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=7ea19dcafb8d373732158eb48adbf7bfc8d8ba27;p=platform%2Fupstream%2Fgcc.git IBM Z: Rename mode attr tointvec to TOINTVEC Just a preparation to add a lower-case tointvec. gcc/ChangeLog: * config/s390/vector.md: Rename tointvec to TOINTVEC. * config/s390/vx-builtins.md: Likewise. --- diff --git a/gcc/config/s390/vector.md b/gcc/config/s390/vector.md index 31d3239..58b8999 100644 --- a/gcc/config/s390/vector.md +++ b/gcc/config/s390/vector.md @@ -137,7 +137,7 @@ ; Resulting mode of a vector comparison. For floating point modes an ; integer vector mode with the same element size is picked. -(define_mode_attr tointvec [(V1QI "V1QI") (V2QI "V2QI") (V4QI "V4QI") (V8QI "V8QI") (V16QI "V16QI") +(define_mode_attr TOINTVEC [(V1QI "V1QI") (V2QI "V2QI") (V4QI "V4QI") (V8QI "V8QI") (V16QI "V16QI") (V1HI "V1HI") (V2HI "V2HI") (V4HI "V4HI") (V8HI "V8HI") (V1SI "V1SI") (V2SI "V2SI") (V4SI "V4SI") (V1DI "V1DI") (V2DI "V2DI") @@ -697,12 +697,12 @@ (define_expand "vcond_mask_" [(set (match_operand:V 0 "register_operand" "") (if_then_else:V - (eq (match_operand: 3 "register_operand" "") + (eq (match_operand: 3 "register_operand" "") (match_dup 4)) (match_operand:V 2 "register_operand" "") (match_operand:V 1 "register_operand" "")))] "TARGET_VX" - "operands[4] = CONST0_RTX (mode);") + "operands[4] = CONST0_RTX (mode);") ; We only have HW support for byte vectors. The middle-end is @@ -1586,8 +1586,8 @@ ; vfcesb, vfcedb, wfcexb: non-signaling "==" comparison (a == b) (define_insn "*vec_cmpeq_quiet_nocc" - [(set (match_operand: 0 "register_operand" "=v") - (eq: (match_operand:VFT 1 "register_operand" "v") + [(set (match_operand: 0 "register_operand" "=v") + (eq: (match_operand:VFT 1 "register_operand" "v") (match_operand:VFT 2 "register_operand" "v")))] "TARGET_VX" "fceb\t%v0,%v1,%v2" @@ -1595,45 +1595,45 @@ ; vfchsb, vfchdb, wfchxb: non-signaling > comparison (!(b u>= a)) (define_insn "vec_cmpgt_quiet_nocc" - [(set (match_operand: 0 "register_operand" "=v") - (not: - (unge: (match_operand:VFT 2 "register_operand" "v") + [(set (match_operand: 0 "register_operand" "=v") + (not: + (unge: (match_operand:VFT 2 "register_operand" "v") (match_operand:VFT 1 "register_operand" "v"))))] "TARGET_VX" "fchb\t%v0,%v1,%v2" [(set_attr "op_type" "VRR")]) (define_expand "vec_cmplt_quiet_nocc" - [(set (match_operand: 0 "register_operand" "=v") - (not: - (unge: (match_operand:VFT 1 "register_operand" "v") + [(set (match_operand: 0 "register_operand" "=v") + (not: + (unge: (match_operand:VFT 1 "register_operand" "v") (match_operand:VFT 2 "register_operand" "v"))))] "TARGET_VX") ; vfchesb, vfchedb, wfchexb: non-signaling >= comparison (!(a u< b)) (define_insn "vec_cmpge_quiet_nocc" - [(set (match_operand: 0 "register_operand" "=v") - (not: - (unlt: (match_operand:VFT 1 "register_operand" "v") + [(set (match_operand: 0 "register_operand" "=v") + (not: + (unlt: (match_operand:VFT 1 "register_operand" "v") (match_operand:VFT 2 "register_operand" "v"))))] "TARGET_VX" "fcheb\t%v0,%v1,%v2" [(set_attr "op_type" "VRR")]) (define_expand "vec_cmple_quiet_nocc" - [(set (match_operand: 0 "register_operand" "=v") - (not: - (unlt: (match_operand:VFT 2 "register_operand" "v") + [(set (match_operand: 0 "register_operand" "=v") + (not: + (unlt: (match_operand:VFT 2 "register_operand" "v") (match_operand:VFT 1 "register_operand" "v"))))] "TARGET_VX") ; vfkesb, vfkedb, wfkexb: signaling == comparison ((a >= b) & (b >= a)) (define_insn "*vec_cmpeq_signaling_nocc" - [(set (match_operand: 0 "register_operand" "=v") - (and: - (ge: (match_operand:VFT 1 "register_operand" "v") + [(set (match_operand: 0 "register_operand" "=v") + (and: + (ge: (match_operand:VFT 1 "register_operand" "v") (match_operand:VFT 2 "register_operand" "v")) - (ge: (match_dup 2) + (ge: (match_dup 2) (match_dup 1))))] "TARGET_VXE" "fkeb\t%v0,%v1,%v2" @@ -1641,16 +1641,16 @@ ; vfkhsb, vfkhdb, wfkhxb: signaling > comparison (a > b) (define_insn "*vec_cmpgt_signaling_nocc" - [(set (match_operand: 0 "register_operand" "=v") - (gt: (match_operand:VFT 1 "register_operand" "v") + [(set (match_operand: 0 "register_operand" "=v") + (gt: (match_operand:VFT 1 "register_operand" "v") (match_operand:VFT 2 "register_operand" "v")))] "TARGET_VXE" "fkhb\t%v0,%v1,%v2" [(set_attr "op_type" "VRR")]) (define_insn "*vec_cmpgt_signaling_finite_nocc" - [(set (match_operand: 0 "register_operand" "=v") - (gt: (match_operand:VFT 1 "register_operand" "v") + [(set (match_operand: 0 "register_operand" "=v") + (gt: (match_operand:VFT 1 "register_operand" "v") (match_operand:VFT 2 "register_operand" "v")))] "TARGET_NONSIGNALING_VECTOR_COMPARE_OK" "fchb\t%v0,%v1,%v2" @@ -1658,16 +1658,16 @@ ; vfkhesb, vfkhedb, wfkhexb: signaling >= comparison (a >= b) (define_insn "*vec_cmpge_signaling_nocc" - [(set (match_operand: 0 "register_operand" "=v") - (ge: (match_operand:VFT 1 "register_operand" "v") + [(set (match_operand: 0 "register_operand" "=v") + (ge: (match_operand:VFT 1 "register_operand" "v") (match_operand:VFT 2 "register_operand" "v")))] "TARGET_VXE" "fkheb\t%v0,%v1,%v2" [(set_attr "op_type" "VRR")]) (define_insn "*vec_cmpge_signaling_finite_nocc" - [(set (match_operand: 0 "register_operand" "=v") - (ge: (match_operand:VFT 1 "register_operand" "v") + [(set (match_operand: 0 "register_operand" "=v") + (ge: (match_operand:VFT 1 "register_operand" "v") (match_operand:VFT 2 "register_operand" "v")))] "TARGET_NONSIGNALING_VECTOR_COMPARE_OK" "fcheb\t%v0,%v1,%v2" @@ -1679,84 +1679,84 @@ ; UNGT a u> b -> !!(b u< a) (define_expand "vec_cmpungt" - [(set (match_operand: 0 "register_operand" "=v") - (not: - (unlt: (match_operand:VFT 2 "register_operand" "v") + [(set (match_operand: 0 "register_operand" "=v") + (not: + (unlt: (match_operand:VFT 2 "register_operand" "v") (match_operand:VFT 1 "register_operand" "v")))) (set (match_dup 0) - (not: (match_dup 0)))] + (not: (match_dup 0)))] "TARGET_VX") ; UNGE a u>= b -> !!(a u>= b) (define_expand "vec_cmpunge" - [(set (match_operand: 0 "register_operand" "=v") - (not: - (unge: (match_operand:VFT 1 "register_operand" "v") + [(set (match_operand: 0 "register_operand" "=v") + (not: + (unge: (match_operand:VFT 1 "register_operand" "v") (match_operand:VFT 2 "register_operand" "v")))) (set (match_dup 0) - (not: (match_dup 0)))] + (not: (match_dup 0)))] "TARGET_VX") ; UNEQ a u== b -> !(!(a u>= b) | !(b u>= a)) (define_expand "vec_cmpuneq" - [(set (match_operand: 0 "register_operand" "=v") - (not: - (unge: (match_operand:VFT 1 "register_operand" "v") + [(set (match_operand: 0 "register_operand" "=v") + (not: + (unge: (match_operand:VFT 1 "register_operand" "v") (match_operand:VFT 2 "register_operand" "v")))) (set (match_dup 3) - (not: - (unge: (match_dup 2) + (not: + (unge: (match_dup 2) (match_dup 1)))) (set (match_dup 0) - (ior: (match_dup 0) + (ior: (match_dup 0) (match_dup 3))) (set (match_dup 0) - (not: (match_dup 0)))] + (not: (match_dup 0)))] "TARGET_VX" { - operands[3] = gen_reg_rtx (mode); + operands[3] = gen_reg_rtx (mode); }) ; LTGT a <> b -> a > b | b > a (define_expand "vec_cmpltgt" - [(set (match_operand: 0 "register_operand" "=v") - (gt: (match_operand:VFT 1 "register_operand" "v") + [(set (match_operand: 0 "register_operand" "=v") + (gt: (match_operand:VFT 1 "register_operand" "v") (match_operand:VFT 2 "register_operand" "v"))) - (set (match_dup 3) (gt: (match_dup 2) (match_dup 1))) - (set (match_dup 0) (ior: (match_dup 0) (match_dup 3)))] + (set (match_dup 3) (gt: (match_dup 2) (match_dup 1))) + (set (match_dup 0) (ior: (match_dup 0) (match_dup 3)))] "TARGET_VXE" { - operands[3] = gen_reg_rtx (mode); + operands[3] = gen_reg_rtx (mode); }) ; ORDERED (a, b): !(a u< b) | !(a u>= b) (define_expand "vec_cmpordered" - [(set (match_operand: 0 "register_operand" "=v") - (not: - (unlt: (match_operand:VFT 1 "register_operand" "v") + [(set (match_operand: 0 "register_operand" "=v") + (not: + (unlt: (match_operand:VFT 1 "register_operand" "v") (match_operand:VFT 2 "register_operand" "v")))) (set (match_dup 3) - (not: - (unge: (match_dup 1) + (not: + (unge: (match_dup 1) (match_dup 2)))) (set (match_dup 0) - (ior: (match_dup 0) + (ior: (match_dup 0) (match_dup 3)))] "TARGET_VX" { - operands[3] = gen_reg_rtx (mode); + operands[3] = gen_reg_rtx (mode); }) ; UNORDERED (a, b): !ORDERED (a, b) (define_expand "vec_cmpunordered" - [(match_operand: 0 "register_operand" "=v") + [(match_operand: 0 "register_operand" "=v") (match_operand:VFT 1 "register_operand" "v") (match_operand:VFT 2 "register_operand" "v")] "TARGET_VX" { emit_insn (gen_vec_cmpordered (operands[0], operands[1], operands[2])); emit_insn (gen_rtx_SET (operands[0], - gen_rtx_NOT (mode, operands[0]))); + gen_rtx_NOT (mode, operands[0]))); DONE; }) @@ -1835,7 +1835,7 @@ (define_split [(set (match_operand:V 0 "register_operand" "") (if_then_else:V - (eq (match_operand: 3 "register_operand" "") + (eq (match_operand: 3 "register_operand" "") (match_operand:V 4 "const0_operand" "")) (match_operand:V 1 "const0_operand" "") (match_operand:V 2 "all_ones_operand" "")))] @@ -1849,7 +1849,7 @@ (define_split [(set (match_operand:V 0 "register_operand" "") (if_then_else:V - (eq (match_operand: 3 "register_operand" "") + (eq (match_operand: 3 "register_operand" "") (match_operand:V 4 "const0_operand" "")) (match_operand:V 1 "all_ones_operand" "") (match_operand:V 2 "const0_operand" "")))] @@ -1863,7 +1863,7 @@ (define_split [(set (match_operand:V 0 "register_operand" "") (if_then_else:V - (ne (match_operand: 3 "register_operand" "") + (ne (match_operand: 3 "register_operand" "") (match_operand:V 4 "const0_operand" "")) (match_operand:V 1 "all_ones_operand" "") (match_operand:V 2 "const0_operand" "")))] @@ -1877,7 +1877,7 @@ (define_split [(set (match_operand:V 0 "register_operand" "") (if_then_else:V - (ne (match_operand: 3 "register_operand" "") + (ne (match_operand: 3 "register_operand" "") (match_operand:V 4 "const0_operand" "")) (match_operand:V 1 "const0_operand" "") (match_operand:V 2 "all_ones_operand" "")))] @@ -1891,8 +1891,8 @@ (define_insn "*vec_sel0" [(set (match_operand:V 0 "register_operand" "=v") (if_then_else:V - (eq (match_operand: 3 "register_operand" "v") - (match_operand: 4 "const0_operand" "")) + (eq (match_operand: 3 "register_operand" "v") + (match_operand: 4 "const0_operand" "")) (match_operand:V 1 "register_operand" "v") (match_operand:V 2 "register_operand" "v")))] "TARGET_VX" @@ -1903,8 +1903,8 @@ (define_insn "*vec_sel0" [(set (match_operand:V 0 "register_operand" "=v") (if_then_else:V - (eq (not: (match_operand: 3 "register_operand" "v")) - (match_operand: 4 "const0_operand" "")) + (eq (not: (match_operand: 3 "register_operand" "v")) + (match_operand: 4 "const0_operand" "")) (match_operand:V 1 "register_operand" "v") (match_operand:V 2 "register_operand" "v")))] "TARGET_VX" @@ -1915,8 +1915,8 @@ (define_insn "*vec_sel1" [(set (match_operand:V 0 "register_operand" "=v") (if_then_else:V - (eq (match_operand: 3 "register_operand" "v") - (match_operand: 4 "all_ones_operand" "")) + (eq (match_operand: 3 "register_operand" "v") + (match_operand: 4 "all_ones_operand" "")) (match_operand:V 1 "register_operand" "v") (match_operand:V 2 "register_operand" "v")))] "TARGET_VX" @@ -1927,8 +1927,8 @@ (define_insn "*vec_sel1" [(set (match_operand:V 0 "register_operand" "=v") (if_then_else:V - (eq (not: (match_operand: 3 "register_operand" "v")) - (match_operand: 4 "all_ones_operand" "")) + (eq (not: (match_operand: 3 "register_operand" "v")) + (match_operand: 4 "all_ones_operand" "")) (match_operand:V 1 "register_operand" "v") (match_operand:V 2 "register_operand" "v")))] "TARGET_VX" diff --git a/gcc/config/s390/vx-builtins.md b/gcc/config/s390/vx-builtins.md index 010db4d..2bbed19 100644 --- a/gcc/config/s390/vx-builtins.md +++ b/gcc/config/s390/vx-builtins.md @@ -76,7 +76,7 @@ (define_insn "vec_gather_element" [(set (match_operand:V_HW_32_64 0 "register_operand" "=v") (unspec:V_HW_32_64 [(match_operand:V_HW_32_64 1 "register_operand" "0") - (match_operand: 2 "register_operand" "v") + (match_operand: 2 "register_operand" "v") (match_operand:BLK 3 "memory_operand" "R") (match_operand:QI 4 "const_mask_operand" "C")] UNSPEC_VEC_GATHER))] @@ -477,7 +477,7 @@ (define_insn "vec_scatter_element_" [(set (mem: (plus: (unspec: - [(match_operand: 1 "register_operand" "v") + [(match_operand: 1 "register_operand" "v") (match_operand:QI 3 "const_mask_operand" "C")] UNSPEC_VEC_EXTRACT) (match_operand:DI 2 "address_operand" "ZQ"))) @@ -492,7 +492,7 @@ ; multiplexing here in the expander. (define_expand "vec_scatter_element" [(match_operand:V_HW_32_64 0 "register_operand" "") - (match_operand: 1 "register_operand" "") + (match_operand: 1 "register_operand" "") (match_operand 2 "address_operand" "") (match_operand:QI 3 "const_mask_operand" "")] "TARGET_VX" @@ -813,8 +813,8 @@ }) (define_expand "vec_cmp" - [(set (match_operand: 0 "register_operand" "=v") - (fpcmp: (match_operand:VF_HW 1 "register_operand" "v") + [(set (match_operand: 0 "register_operand" "=v") + (fpcmp: (match_operand:VF_HW 1 "register_operand" "v") (match_operand:VF_HW 2 "register_operand" "v")))] "TARGET_VX" { @@ -1050,7 +1050,7 @@ (define_expand "vec_slb" [(set (match_operand:V_HW 0 "register_operand" "") (unspec:V_HW [(match_operand:V_HW 1 "register_operand" "") - (match_operand: 2 "register_operand" "")] + (match_operand: 2 "register_operand" "")] UNSPEC_VEC_SLB))] "TARGET_VX" { @@ -1121,7 +1121,7 @@ (define_insn "vec_srab" [(set (match_operand:V_HW 0 "register_operand" "=v") (unspec:V_HW [(match_operand:V_HW 1 "register_operand" "v") - (match_operand: 2 "register_operand" "v")] + (match_operand: 2 "register_operand" "v")] UNSPEC_VEC_SRAB))] "TARGET_VX" "vsrab\t%v0,%v1,%v2" @@ -1146,7 +1146,7 @@ (define_expand "vec_srb" [(set (match_operand:V_HW 0 "register_operand" "") (unspec:V_HW [(match_operand:V_HW 1 "register_operand" "") - (match_operand: 2 "register_operand" "")] + (match_operand: 2 "register_operand" "")] UNSPEC_VEC_SRLB))] "TARGET_VX" { @@ -1229,7 +1229,7 @@ (define_expand "vec_test_mask_int" [(set (reg:CCRAW CC_REGNUM) (unspec:CCRAW [(match_operand:V_HW 1 "register_operand" "") - (match_operand: 2 "register_operand" "")] + (match_operand: 2 "register_operand" "")] UNSPEC_VEC_TEST_MASK)) (set (match_operand:SI 0 "register_operand" "") (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))] @@ -1238,7 +1238,7 @@ (define_insn "*vec_test_mask" [(set (reg:CCRAW CC_REGNUM) (unspec:CCRAW [(match_operand:V_HW 0 "register_operand" "v") - (match_operand: 1 "register_operand" "v")] + (match_operand: 1 "register_operand" "v")] UNSPEC_VEC_TEST_MASK))] "TARGET_VX" "vtm\t%v0,%v1" @@ -1946,7 +1946,7 @@ (unspec:CCRAW [(match_operand:VF_HW 1 "register_operand" "v") (match_operand:HI 2 "const_int_operand" "J")] UNSPEC_VEC_VFTCICC)) - (clobber (match_scratch: 0 "=v"))] + (clobber (match_scratch: 0 "=v"))] "TARGET_VX && CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'J', \"J\")" "ftcib\t%v0,%v1,%x2" [(set_attr "op_type" "VRR")]) @@ -1957,7 +1957,7 @@ (unspec:CCRAW [(match_operand:VF_HW 0 "register_operand") (match_operand:HI 1 "const_int_operand")] UNSPEC_VEC_VFTCICC)) - (clobber (scratch:))]) + (clobber (scratch:))]) (set (match_operand:SI 2 "register_operand" "") (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))] "TARGET_VX && CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[1]), 'J', \"J\")") @@ -2083,7 +2083,7 @@ [(set (reg:VFCMP CC_REGNUM) (compare:VFCMP (match_operand:VF_HW 0 "register_operand" "v") (match_operand:VF_HW 1 "register_operand" "v"))) - (clobber (match_scratch: 2 "=v"))] + (clobber (match_scratch: 2 "=v"))] "TARGET_VX" "fcbs\t%v2,%v0,%v1" [(set_attr "op_type" "VRR")]) @@ -2094,8 +2094,8 @@ [(set (reg:CCVEQ CC_REGNUM) (compare:CCVEQ (match_operand:VF_HW 1 "register_operand" "v") (match_operand:VF_HW 2 "register_operand" "v"))) - (set (match_operand: 0 "register_operand" "=v") - (eq: (match_dup 1) (match_dup 2)))]) + (set (match_operand: 0 "register_operand" "=v") + (eq: (match_dup 1) (match_dup 2)))]) (set (match_operand:SI 3 "memory_operand" "") (unspec:SI [(reg:CCVEQ CC_REGNUM)] UNSPEC_CC_TO_INT))] "TARGET_VX") @@ -2105,8 +2105,8 @@ [(set (reg:CCVFH CC_REGNUM) (compare:CCVFH (match_operand:VF_HW 1 "register_operand" "v") (match_operand:VF_HW 2 "register_operand" "v"))) - (set (match_operand: 0 "register_operand" "=v") - (gt: (match_dup 1) (match_dup 2)))]) + (set (match_operand: 0 "register_operand" "=v") + (gt: (match_dup 1) (match_dup 2)))]) (set (match_operand:SI 3 "memory_operand" "") (unspec:SI [(reg:CCVIH CC_REGNUM)] UNSPEC_CC_TO_INT))] "TARGET_VX") @@ -2116,8 +2116,8 @@ [(set (reg:CCVFHE CC_REGNUM) (compare:CCVFHE (match_operand:VF_HW 1 "register_operand" "v") (match_operand:VF_HW 2 "register_operand" "v"))) - (set (match_operand: 0 "register_operand" "=v") - (ge: (match_dup 1) (match_dup 2)))]) + (set (match_operand: 0 "register_operand" "=v") + (ge: (match_dup 1) (match_dup 2)))]) (set (match_operand:SI 3 "memory_operand" "") (unspec:SI [(reg:CCVFHE CC_REGNUM)] UNSPEC_CC_TO_INT))] "TARGET_VX") @@ -2131,8 +2131,8 @@ [(set (reg:CCVEQ CC_REGNUM) (compare:CCVEQ (match_operand:VF_HW 0 "register_operand" "v") (match_operand:VF_HW 1 "register_operand" "v"))) - (set (match_operand: 2 "register_operand" "=v") - (eq: (match_dup 0) (match_dup 1)))] + (set (match_operand: 2 "register_operand" "=v") + (eq: (match_dup 0) (match_dup 1)))] "TARGET_VX" "fcebs\t%v2,%v0,%v1" [(set_attr "op_type" "VRR")]) @@ -2142,8 +2142,8 @@ [(set (reg:CCVFH CC_REGNUM) (compare:CCVFH (match_operand:VF_HW 0 "register_operand" "v") (match_operand:VF_HW 1 "register_operand" "v"))) - (set (match_operand: 2 "register_operand" "=v") - (gt: (match_dup 0) (match_dup 1)))] + (set (match_operand: 2 "register_operand" "=v") + (gt: (match_dup 0) (match_dup 1)))] "TARGET_VX" "fchbs\t%v2,%v0,%v1" [(set_attr "op_type" "VRR")]) @@ -2153,8 +2153,8 @@ [(set (reg:CCVFHE CC_REGNUM) (compare:CCVFHE (match_operand:VF_HW 0 "register_operand" "v") (match_operand:VF_HW 1 "register_operand" "v"))) - (set (match_operand: 2 "register_operand" "=v") - (ge: (match_dup 0) (match_dup 1)))] + (set (match_operand: 2 "register_operand" "=v") + (ge: (match_dup 0) (match_dup 1)))] "TARGET_VX" "fchebs\t%v2,%v0,%v1" [(set_attr "op_type" "VRR")])