From: Thomas Lively <tlively@google.com>
Date: Wed, 16 Mar 2022 20:34:56 +0000 (-0700)
Subject: [WebAssembly] Fix names of SIMD instructions containing '_zero'
X-Git-Tag: upstream/15.0.7~13388
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=7e8913d775ca2959861425dca886f98ac03ab9b4;p=platform%2Fupstream%2Fllvm.git

[WebAssembly] Fix names of SIMD instructions containing '_zero'

Fix the instruction names to match the WebAssembly spec:

 - `i32x4.trunc_sat_zero_f64x2_{s,u}` => `i32x4.trunc_sat_f64x2_{s,u}_zero`
 - `f32x4.demote_zero_f64x2` => `f32x4.demote_f64x2_zero`

Also rename related things like intrinsics, builtins, and test functions to
match.

Reviewed By: aheejin

Differential Revision: https://reviews.llvm.org/D121661
---

diff --git a/clang/include/clang/Basic/BuiltinsWebAssembly.def b/clang/include/clang/Basic/BuiltinsWebAssembly.def
index 057d968..24fb24f 100644
--- a/clang/include/clang/Basic/BuiltinsWebAssembly.def
+++ b/clang/include/clang/Basic/BuiltinsWebAssembly.def
@@ -158,8 +158,8 @@ TARGET_BUILTIN(__builtin_wasm_narrow_u_i8x16_i16x8, "V16UcV8sV8s", "nc", "simd12
 TARGET_BUILTIN(__builtin_wasm_narrow_s_i16x8_i32x4, "V8sV4iV4i", "nc", "simd128")
 TARGET_BUILTIN(__builtin_wasm_narrow_u_i16x8_i32x4, "V8UsV4iV4i", "nc", "simd128")
 
-TARGET_BUILTIN(__builtin_wasm_trunc_sat_zero_s_f64x2_i32x4, "V4iV2d", "nc", "simd128")
-TARGET_BUILTIN(__builtin_wasm_trunc_sat_zero_u_f64x2_i32x4, "V4UiV2d", "nc", "simd128")
+TARGET_BUILTIN(__builtin_wasm_trunc_sat_s_zero_f64x2_i32x4, "V4iV2d", "nc", "simd128")
+TARGET_BUILTIN(__builtin_wasm_trunc_sat_u_zero_f64x2_i32x4, "V4UiV2d", "nc", "simd128")
 
 // Relaxed SIMD builtins (experimental)
 TARGET_BUILTIN(__builtin_wasm_fma_f32x4, "V4fV4fV4fV4f", "nc", "relaxed-simd")
@@ -181,8 +181,8 @@ TARGET_BUILTIN(__builtin_wasm_relaxed_max_f64x2, "V2dV2dV2d", "nc", "relaxed-sim
 
 TARGET_BUILTIN(__builtin_wasm_relaxed_trunc_s_i32x4_f32x4, "V4iV4f", "nc", "relaxed-simd")
 TARGET_BUILTIN(__builtin_wasm_relaxed_trunc_u_i32x4_f32x4, "V4UiV4f", "nc", "relaxed-simd")
-TARGET_BUILTIN(__builtin_wasm_relaxed_trunc_zero_s_i32x4_f64x2, "V4iV2d", "nc", "relaxed-simd")
-TARGET_BUILTIN(__builtin_wasm_relaxed_trunc_zero_u_i32x4_f64x2, "V4UiV2d", "nc", "relaxed-simd")
+TARGET_BUILTIN(__builtin_wasm_relaxed_trunc_s_zero_i32x4_f64x2, "V4iV2d", "nc", "relaxed-simd")
+TARGET_BUILTIN(__builtin_wasm_relaxed_trunc_u_zero_i32x4_f64x2, "V4UiV2d", "nc", "relaxed-simd")
 
 #undef BUILTIN
 #undef TARGET_BUILTIN
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index 6383dfd..bdb430c 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -18411,15 +18411,15 @@ Value *CodeGenFunction::EmitWebAssemblyBuiltinExpr(unsigned BuiltinID,
         CGM.getIntrinsic(IntNo, {ConvertType(E->getType()), Low->getType()});
     return Builder.CreateCall(Callee, {Low, High});
   }
-  case WebAssembly::BI__builtin_wasm_trunc_sat_zero_s_f64x2_i32x4:
-  case WebAssembly::BI__builtin_wasm_trunc_sat_zero_u_f64x2_i32x4: {
+  case WebAssembly::BI__builtin_wasm_trunc_sat_s_zero_f64x2_i32x4:
+  case WebAssembly::BI__builtin_wasm_trunc_sat_u_zero_f64x2_i32x4: {
     Value *Vec = EmitScalarExpr(E->getArg(0));
     unsigned IntNo;
     switch (BuiltinID) {
-    case WebAssembly::BI__builtin_wasm_trunc_sat_zero_s_f64x2_i32x4:
+    case WebAssembly::BI__builtin_wasm_trunc_sat_s_zero_f64x2_i32x4:
       IntNo = Intrinsic::fptosi_sat;
       break;
-    case WebAssembly::BI__builtin_wasm_trunc_sat_zero_u_f64x2_i32x4:
+    case WebAssembly::BI__builtin_wasm_trunc_sat_u_zero_f64x2_i32x4:
       IntNo = Intrinsic::fptoui_sat;
       break;
     default:
@@ -18510,8 +18510,8 @@ Value *CodeGenFunction::EmitWebAssemblyBuiltinExpr(unsigned BuiltinID,
   }
   case WebAssembly::BI__builtin_wasm_relaxed_trunc_s_i32x4_f32x4:
   case WebAssembly::BI__builtin_wasm_relaxed_trunc_u_i32x4_f32x4:
-  case WebAssembly::BI__builtin_wasm_relaxed_trunc_zero_s_i32x4_f64x2:
-  case WebAssembly::BI__builtin_wasm_relaxed_trunc_zero_u_i32x4_f64x2: {
+  case WebAssembly::BI__builtin_wasm_relaxed_trunc_s_zero_i32x4_f64x2:
+  case WebAssembly::BI__builtin_wasm_relaxed_trunc_u_zero_i32x4_f64x2: {
     Value *Vec = EmitScalarExpr(E->getArg(0));
     unsigned IntNo;
     switch (BuiltinID) {
@@ -18521,11 +18521,11 @@ Value *CodeGenFunction::EmitWebAssemblyBuiltinExpr(unsigned BuiltinID,
     case WebAssembly::BI__builtin_wasm_relaxed_trunc_u_i32x4_f32x4:
       IntNo = Intrinsic::wasm_relaxed_trunc_unsigned;
       break;
-    case WebAssembly::BI__builtin_wasm_relaxed_trunc_zero_s_i32x4_f64x2:
-      IntNo = Intrinsic::wasm_relaxed_trunc_zero_signed;
+    case WebAssembly::BI__builtin_wasm_relaxed_trunc_s_zero_i32x4_f64x2:
+      IntNo = Intrinsic::wasm_relaxed_trunc_signed_zero;
       break;
-    case WebAssembly::BI__builtin_wasm_relaxed_trunc_zero_u_i32x4_f64x2:
-      IntNo = Intrinsic::wasm_relaxed_trunc_zero_unsigned;
+    case WebAssembly::BI__builtin_wasm_relaxed_trunc_u_zero_i32x4_f64x2:
+      IntNo = Intrinsic::wasm_relaxed_trunc_unsigned_zero;
       break;
     default:
       llvm_unreachable("unexpected builtin ID");
diff --git a/clang/lib/Headers/wasm_simd128.h b/clang/lib/Headers/wasm_simd128.h
index 3889a27..f93de12 100644
--- a/clang/lib/Headers/wasm_simd128.h
+++ b/clang/lib/Headers/wasm_simd128.h
@@ -1405,12 +1405,12 @@ wasm_f64x2_convert_low_u32x4(v128_t __a) {
 
 static __inline__ v128_t __DEFAULT_FN_ATTRS
 wasm_i32x4_trunc_sat_f64x2_zero(v128_t __a) {
-  return (v128_t)__builtin_wasm_trunc_sat_zero_s_f64x2_i32x4((__f64x2)__a);
+  return (v128_t)__builtin_wasm_trunc_sat_s_zero_f64x2_i32x4((__f64x2)__a);
 }
 
 static __inline__ v128_t __DEFAULT_FN_ATTRS
 wasm_u32x4_trunc_sat_f64x2_zero(v128_t __a) {
-  return (v128_t)__builtin_wasm_trunc_sat_zero_u_f64x2_i32x4((__f64x2)__a);
+  return (v128_t)__builtin_wasm_trunc_sat_u_zero_f64x2_i32x4((__f64x2)__a);
 }
 
 static __inline__ v128_t __DEFAULT_FN_ATTRS
diff --git a/clang/test/CodeGen/builtins-wasm.c b/clang/test/CodeGen/builtins-wasm.c
index f1f5ccf..045274d 100644
--- a/clang/test/CodeGen/builtins-wasm.c
+++ b/clang/test/CodeGen/builtins-wasm.c
@@ -636,15 +636,15 @@ u16x8 narrow_u_i16x8_i32x4(i32x4 low, i32x4 high) {
   // WEBASSEMBLY: ret
 }
 
-i32x4 trunc_sat_zero_s_f64x2_i32x4(f64x2 x) {
-  return __builtin_wasm_trunc_sat_zero_s_f64x2_i32x4(x);
+i32x4 trunc_sat_s_zero_f64x2_i32x4(f64x2 x) {
+  return __builtin_wasm_trunc_sat_s_zero_f64x2_i32x4(x);
   // WEBASSEMBLY: %0 = tail call <2 x i32> @llvm.fptosi.sat.v2i32.v2f64(<2 x double> %x)
   // WEBASSEMBLY: %1 = shufflevector <2 x i32> %0, <2 x i32> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
   // WEBASSEMBLY: ret <4 x i32> %1
 }
 
-u32x4 trunc_sat_zero_u_f64x2_i32x4(f64x2 x) {
-  return __builtin_wasm_trunc_sat_zero_u_f64x2_i32x4(x);
+u32x4 trunc_sat_u_zero_f64x2_i32x4(f64x2 x) {
+  return __builtin_wasm_trunc_sat_u_zero_f64x2_i32x4(x);
   // WEBASSEMBLY: %0 = tail call <2 x i32> @llvm.fptoui.sat.v2i32.v2f64(<2 x double> %x)
   // WEBASSEMBLY: %1 = shufflevector <2 x i32> %0, <2 x i32> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
   // WEBASSEMBLY: ret <4 x i32> %1
@@ -766,14 +766,14 @@ u32x4 relaxed_trunc_u_i32x4_f32x4(f32x4 f) {
   // WEBASSEMBLY-NEXT: ret
 }
 
-i32x4 relaxed_trunc_zero_s_i32x4_f64x2(f64x2 x) {
-  return __builtin_wasm_relaxed_trunc_zero_s_i32x4_f64x2(x);
-  // WEBASSEMBLY: call <4 x i32> @llvm.wasm.relaxed.trunc.zero.signed(<2 x double> %x)
+i32x4 relaxed_trunc_s_zero_i32x4_f64x2(f64x2 x) {
+  return __builtin_wasm_relaxed_trunc_s_zero_i32x4_f64x2(x);
+  // WEBASSEMBLY: call <4 x i32> @llvm.wasm.relaxed.trunc.signed.zero(<2 x double> %x)
   // WEBASSEMBLY-NEXT: ret
 }
 
-u32x4 relaxed_trunc_zero_u_i32x4_f64x2(f64x2 x) {
-  return __builtin_wasm_relaxed_trunc_zero_u_i32x4_f64x2(x);
-  // WEBASSEMBLY: call <4 x i32> @llvm.wasm.relaxed.trunc.zero.unsigned(<2 x double> %x)
+u32x4 relaxed_trunc_u_zero_i32x4_f64x2(f64x2 x) {
+  return __builtin_wasm_relaxed_trunc_u_zero_i32x4_f64x2(x);
+  // WEBASSEMBLY: call <4 x i32> @llvm.wasm.relaxed.trunc.unsigned.zero(<2 x double> %x)
   // WEBASSEMBLY-NEXT: ret
 }
diff --git a/llvm/include/llvm/IR/IntrinsicsWebAssembly.td b/llvm/include/llvm/IR/IntrinsicsWebAssembly.td
index aecc3d9..5436f45 100644
--- a/llvm/include/llvm/IR/IntrinsicsWebAssembly.td
+++ b/llvm/include/llvm/IR/IntrinsicsWebAssembly.td
@@ -256,12 +256,12 @@ def int_wasm_relaxed_trunc_unsigned:
             [llvm_v4f32_ty],
             [IntrNoMem, IntrSpeculatable]>;
 
-def int_wasm_relaxed_trunc_zero_signed:
+def int_wasm_relaxed_trunc_signed_zero:
   Intrinsic<[llvm_v4i32_ty],
             [llvm_v2f64_ty],
             [IntrNoMem, IntrSpeculatable]>;
 
-def int_wasm_relaxed_trunc_zero_unsigned:
+def int_wasm_relaxed_trunc_unsigned_zero:
   Intrinsic<[llvm_v4i32_ty],
             [llvm_v2f64_ty],
             [IntrNoMem, IntrSpeculatable]>;
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td b/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
index 5bb12c7..449a44f 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
@@ -1229,9 +1229,9 @@ def trunc_sat_zero_s :
   SDNode<"WebAssemblyISD::TRUNC_SAT_ZERO_S", trunc_sat_zero_t>;
 def trunc_sat_zero_u :
   SDNode<"WebAssemblyISD::TRUNC_SAT_ZERO_U", trunc_sat_zero_t>;
-defm "" : SIMDConvert<I32x4, F64x2, trunc_sat_zero_s, "trunc_sat_zero_f64x2_s",
+defm "" : SIMDConvert<I32x4, F64x2, trunc_sat_zero_s, "trunc_sat_f64x2_s_zero",
                       0xfc>;
-defm "" : SIMDConvert<I32x4, F64x2, trunc_sat_zero_u, "trunc_sat_zero_f64x2_u",
+defm "" : SIMDConvert<I32x4, F64x2, trunc_sat_zero_u, "trunc_sat_f64x2_u_zero",
                       0xfd>;
 
 // Integer to floating point: convert
@@ -1307,7 +1307,7 @@ defm "" : SIMDConvert<I32x4, I16x8, int_wasm_extadd_pairwise_unsigned,
 def demote_t : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>]>;
 def demote_zero : SDNode<"WebAssemblyISD::DEMOTE_ZERO", demote_t>;
 defm "" : SIMDConvert<F32x4, F64x2, demote_zero,
-                      "demote_zero_f64x2", 0x5e>;
+                      "demote_f64x2_zero", 0x5e>;
 
 def promote_t : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>]>;
 def promote_low : SDNode<"WebAssemblyISD::PROMOTE_LOW", promote_t>;
@@ -1415,5 +1415,5 @@ multiclass SIMD_RELAXED_CONVERT<Vec vec, Vec arg, SDPatternOperator op, string n
 defm "" : SIMD_RELAXED_CONVERT<I32x4, F32x4, int_wasm_relaxed_trunc_signed, "relaxed_trunc_f32x4_s", 0xa5>;
 defm "" : SIMD_RELAXED_CONVERT<I32x4, F32x4, int_wasm_relaxed_trunc_unsigned, "relaxed_trunc_f32x4_u", 0xa6>;
 
-defm "" : SIMD_RELAXED_CONVERT<I32x4, F64x2, int_wasm_relaxed_trunc_zero_signed, "relaxed_trunc_f64x2_s_zero", 0xc5>;
-defm "" : SIMD_RELAXED_CONVERT<I32x4, F64x2, int_wasm_relaxed_trunc_zero_unsigned, "relaxed_trunc_f64x2_u_zero", 0xc6>;
+defm "" : SIMD_RELAXED_CONVERT<I32x4, F64x2, int_wasm_relaxed_trunc_signed_zero, "relaxed_trunc_f64x2_s_zero", 0xc5>;
+defm "" : SIMD_RELAXED_CONVERT<I32x4, F64x2, int_wasm_relaxed_trunc_unsigned_zero, "relaxed_trunc_f64x2_u_zero", 0xc6>;
diff --git a/llvm/test/CodeGen/WebAssembly/simd-conversions.ll b/llvm/test/CodeGen/WebAssembly/simd-conversions.ll
index aec6b94..6e12d8a 100644
--- a/llvm/test/CodeGen/WebAssembly/simd-conversions.ll
+++ b/llvm/test/CodeGen/WebAssembly/simd-conversions.ll
@@ -211,7 +211,7 @@ define <4 x float> @demote_zero_v4f32(<2 x double> %x) {
 ; CHECK:         .functype demote_zero_v4f32 (v128) -> (v128)
 ; CHECK-NEXT:  # %bb.0:
 ; CHECK-NEXT:    local.get 0
-; CHECK-NEXT:    f32x4.demote_zero_f64x2
+; CHECK-NEXT:    f32x4.demote_f64x2_zero
 ; CHECK-NEXT:    # fallthrough-return
   %v = shufflevector <2 x double> %x, <2 x double> zeroinitializer,
          <4 x i32> <i32 0, i32 1, i32 2, i32 3>
@@ -224,7 +224,7 @@ define <4 x float> @demote_zero_v4f32_2(<2 x double> %x) {
 ; CHECK:         .functype demote_zero_v4f32_2 (v128) -> (v128)
 ; CHECK-NEXT:  # %bb.0:
 ; CHECK-NEXT:    local.get 0
-; CHECK-NEXT:    f32x4.demote_zero_f64x2
+; CHECK-NEXT:    f32x4.demote_f64x2_zero
 ; CHECK-NEXT:    # fallthrough-return
   %v = fptrunc <2 x double> %x to <2 x float>
   %a = shufflevector <2 x float> %v, <2 x float> zeroinitializer,
diff --git a/llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll b/llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll
index a7df54f..8e22549 100644
--- a/llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll
+++ b/llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll
@@ -466,48 +466,48 @@ define <4 x i32> @trunc_sat_u_v4i32(<4 x float> %x) {
   ret <4 x i32> %a
 }
 
-; CHECK-LABEL: trunc_sat_zero_s_v4i32:
-; CHECK-NEXT: .functype trunc_sat_zero_s_v4i32 (v128) -> (v128){{$}}
-; CHECK-NEXT: i32x4.trunc_sat_zero_f64x2_s $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-LABEL: trunc_sat_s_zero_v4i32:
+; CHECK-NEXT: .functype trunc_sat_s_zero_v4i32 (v128) -> (v128){{$}}
+; CHECK-NEXT: i32x4.trunc_sat_f64x2_s_zero $push[[R:[0-9]+]]=, $0{{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <2 x i32> @llvm.fptosi.sat.v2i32.v2f64(<2 x double>)
-define <4 x i32> @trunc_sat_zero_s_v4i32(<2 x double> %x) {
+define <4 x i32> @trunc_sat_s_zero_v4i32(<2 x double> %x) {
   %v = call <2 x i32> @llvm.fptosi.sat.v2i32.v2f64(<2 x double> %x)
   %a = shufflevector <2 x i32> %v, <2 x i32> <i32 0, i32 0>,
            <4 x i32> <i32 0, i32 1, i32 2, i32 3>
   ret <4 x i32> %a
 }
 
-; CHECK-LABEL: trunc_sat_zero_s_v4i32_2:
-; CHECK-NEXT: .functype trunc_sat_zero_s_v4i32_2 (v128) -> (v128){{$}}
-; SLOW-NEXT: i32x4.trunc_sat_zero_f64x2_s $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-LABEL: trunc_sat_s_zero_v4i32_2:
+; CHECK-NEXT: .functype trunc_sat_s_zero_v4i32_2 (v128) -> (v128){{$}}
+; SLOW-NEXT: i32x4.trunc_sat_f64x2_s_zero $push[[R:[0-9]+]]=, $0{{$}}
 ; SLOW-NEXT: return $pop[[R]]{{$}}
 declare <4 x i32> @llvm.fptosi.sat.v4i32.v4f64(<4 x double>)
-define <4 x i32> @trunc_sat_zero_s_v4i32_2(<2 x double> %x) {
+define <4 x i32> @trunc_sat_s_zero_v4i32_2(<2 x double> %x) {
   %v = shufflevector <2 x double> %x, <2 x double> zeroinitializer,
            <4 x i32> <i32 0, i32 1, i32 2, i32 3>
   %a = call <4 x i32> @llvm.fptosi.sat.v4i32.v4f64(<4 x double> %v)
   ret <4 x i32> %a
 }
 
-; CHECK-LABEL: trunc_sat_zero_u_v4i32:
-; CHECK-NEXT: .functype trunc_sat_zero_u_v4i32 (v128) -> (v128){{$}}
-; CHECK-NEXT: i32x4.trunc_sat_zero_f64x2_u $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-LABEL: trunc_sat_u_zero_v4i32:
+; CHECK-NEXT: .functype trunc_sat_u_zero_v4i32 (v128) -> (v128){{$}}
+; CHECK-NEXT: i32x4.trunc_sat_f64x2_u_zero $push[[R:[0-9]+]]=, $0{{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <2 x i32> @llvm.fptoui.sat.v2i32.v2f64(<2 x double>)
-define <4 x i32> @trunc_sat_zero_u_v4i32(<2 x double> %x) {
+define <4 x i32> @trunc_sat_u_zero_v4i32(<2 x double> %x) {
   %v = call <2 x i32> @llvm.fptoui.sat.v2i32.v2f64(<2 x double> %x)
   %a = shufflevector <2 x i32> %v, <2 x i32> <i32 0, i32 0>,
            <4 x i32> <i32 0, i32 1, i32 2, i32 3>
   ret <4 x i32> %a
 }
 
-; CHECK-LABEL: trunc_sat_zero_u_v4i32_2:
-; CHECK-NEXT: .functype trunc_sat_zero_u_v4i32_2 (v128) -> (v128){{$}}
-; SLOW-NEXT: i32x4.trunc_sat_zero_f64x2_u $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-LABEL: trunc_sat_u_zero_v4i32_2:
+; CHECK-NEXT: .functype trunc_sat_u_zero_v4i32_2 (v128) -> (v128){{$}}
+; SLOW-NEXT: i32x4.trunc_sat_f64x2_u_zero $push[[R:[0-9]+]]=, $0{{$}}
 ; SLOW-NEXT: return $pop[[R]]{{$}}
 declare <4 x i32> @llvm.fptoui.sat.v4i32.v4f64(<4 x double>)
-define <4 x i32> @trunc_sat_zero_u_v4i32_2(<2 x double> %x) {
+define <4 x i32> @trunc_sat_u_zero_v4i32_2(<2 x double> %x) {
   %v = shufflevector <2 x double> %x, <2 x double> zeroinitializer,
            <4 x i32> <i32 0, i32 1, i32 2, i32 3>
   %a = call <4 x i32> @llvm.fptoui.sat.v4i32.v4f64(<4 x double> %v)
@@ -548,23 +548,23 @@ define <4 x i32> @relaxed_trunc_u(<4 x float> %x) {
   ret <4 x i32> %a
 }
 
-; CHECK-LABEL: relaxed_trunc_zero_s:
-; CHECK-NEXT: .functype relaxed_trunc_zero_s (v128) -> (v128){{$}}
+; CHECK-LABEL: relaxed_trunc_s_zero:
+; CHECK-NEXT: .functype relaxed_trunc_s_zero (v128) -> (v128){{$}}
 ; CHECK-NEXT: i32x4.relaxed_trunc_f64x2_s_zero $push[[R:[0-9]+]]=, $0{{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
-declare <4 x i32> @llvm.wasm.relaxed.trunc.zero.signed(<2 x double>)
-define <4 x i32> @relaxed_trunc_zero_s(<2 x double> %x) {
-  %a = call <4 x i32> @llvm.wasm.relaxed.trunc.zero.signed(<2 x double> %x)
+declare <4 x i32> @llvm.wasm.relaxed.trunc.signed.zero(<2 x double>)
+define <4 x i32> @relaxed_trunc_s_zero(<2 x double> %x) {
+  %a = call <4 x i32> @llvm.wasm.relaxed.trunc.signed.zero(<2 x double> %x)
   ret <4 x i32> %a
 }
 
-; CHECK-LABEL: relaxed_trunc_zero_u:
-; CHECK-NEXT: .functype relaxed_trunc_zero_u (v128) -> (v128){{$}}
+; CHECK-LABEL: relaxed_trunc_u_zero:
+; CHECK-NEXT: .functype relaxed_trunc_u_zero (v128) -> (v128){{$}}
 ; CHECK-NEXT: i32x4.relaxed_trunc_f64x2_u_zero $push[[R:[0-9]+]]=, $0{{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
-declare <4 x i32> @llvm.wasm.relaxed.trunc.zero.unsigned(<2 x double>)
-define <4 x i32> @relaxed_trunc_zero_u(<2 x double> %x) {
-  %a = call <4 x i32> @llvm.wasm.relaxed.trunc.zero.unsigned(<2 x double> %x)
+declare <4 x i32> @llvm.wasm.relaxed.trunc.unsigned.zero(<2 x double>)
+define <4 x i32> @relaxed_trunc_u_zero(<2 x double> %x) {
+  %a = call <4 x i32> @llvm.wasm.relaxed.trunc.unsigned.zero(<2 x double> %x)
   ret <4 x i32> %a
 }
 
diff --git a/llvm/test/MC/WebAssembly/simd-encodings.s b/llvm/test/MC/WebAssembly/simd-encodings.s
index f75b46a..9f6c20f 100644
--- a/llvm/test/MC/WebAssembly/simd-encodings.s
+++ b/llvm/test/MC/WebAssembly/simd-encodings.s
@@ -313,8 +313,8 @@ main:
     # CHECK: v128.load64_zero 32 # encoding: [0xfd,0x5d,0x03,0x20]
     v128.load64_zero 32
 
-    # CHECK: f32x4.demote_zero_f64x2 # encoding: [0xfd,0x5e]
-    f32x4.demote_zero_f64x2
+    # CHECK: f32x4.demote_f64x2_zero # encoding: [0xfd,0x5e]
+    f32x4.demote_f64x2_zero
 
     # CHECK: f64x2.promote_low_f32x4 # encoding: [0xfd,0x5f]
     f64x2.promote_low_f32x4
@@ -767,11 +767,11 @@ main:
     # CHECK: f32x4.convert_i32x4_u # encoding: [0xfd,0xfb,0x01]
     f32x4.convert_i32x4_u
 
-    # CHECK: i32x4.trunc_sat_zero_f64x2_s # encoding: [0xfd,0xfc,0x01]
-    i32x4.trunc_sat_zero_f64x2_s
+    # CHECK: i32x4.trunc_sat_f64x2_s_zero # encoding: [0xfd,0xfc,0x01]
+    i32x4.trunc_sat_f64x2_s_zero
 
-    # CHECK: i32x4.trunc_sat_zero_f64x2_u # encoding: [0xfd,0xfd,0x01]
-    i32x4.trunc_sat_zero_f64x2_u
+    # CHECK: i32x4.trunc_sat_f64x2_u_zero # encoding: [0xfd,0xfd,0x01]
+    i32x4.trunc_sat_f64x2_u_zero
 
     # CHECK: f64x2.convert_low_i32x4_s # encoding: [0xfd,0xfe,0x01]
     f64x2.convert_low_i32x4_s