From: Jesse Barnes Date: Wed, 30 Mar 2011 21:08:56 +0000 (-0700) Subject: drm/i915: use i915_enable_rc6 on SNB too X-Git-Tag: v3.12-rc1~5676^2~49^2~33 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=7df8721beb9cbd849dce2b153e3b287c98adbb7f;p=kernel%2Fkernel-generic.git drm/i915: use i915_enable_rc6 on SNB too For debug & testing. Signed-off-by: Jesse Barnes Reviewed-by: Ben Widawsky Signed-off-by: Chris Wilson --- diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 463f753..e99ae3b 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -6959,7 +6959,7 @@ void gen6_enable_rps(struct drm_i915_private *dev_priv) { u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS); - u32 pcu_mbox; + u32 pcu_mbox, rc6_mask = 0; int cur_freq, min_freq, max_freq; int i; @@ -6990,9 +6990,12 @@ void gen6_enable_rps(struct drm_i915_private *dev_priv) I915_WRITE(GEN6_RC6p_THRESHOLD, 100000); I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */ + if (i915_enable_rc6) + rc6_mask = GEN6_RC_CTL_RC6p_ENABLE | + GEN6_RC_CTL_RC6_ENABLE; + I915_WRITE(GEN6_RC_CONTROL, - GEN6_RC_CTL_RC6p_ENABLE | - GEN6_RC_CTL_RC6_ENABLE | + rc6_mask | GEN6_RC_CTL_EI_MODE(1) | GEN6_RC_CTL_HW_ENABLE);