From: Matt Arsenault <Matthew.Arsenault@amd.com>
Date: Mon, 13 Jan 2020 16:02:19 +0000 (-0500)
Subject: AMDGPU/GlobalISel: Simplify assert
X-Git-Tag: llvmorg-11-init~234
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=7d9b0a61c32b95fdc73228266d3f14687a8ada95;p=platform%2Fupstream%2Fllvm.git

AMDGPU/GlobalISel: Simplify assert
---

diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
index 40da393..da94099 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
@@ -144,17 +144,9 @@ AMDGPURegisterBankInfo::AMDGPURegisterBankInfo(const GCNSubtarget &ST)
 
   AlreadyInit = true;
 
-  const RegisterBank &RBSGPR = getRegBank(AMDGPU::SGPRRegBankID);
-  (void)RBSGPR;
-  assert(&RBSGPR == &AMDGPU::SGPRRegBank);
-
-  const RegisterBank &RBVGPR = getRegBank(AMDGPU::VGPRRegBankID);
-  (void)RBVGPR;
-  assert(&RBVGPR == &AMDGPU::VGPRRegBank);
-
-  const RegisterBank &RBAGPR = getRegBank(AMDGPU::AGPRRegBankID);
-  (void)RBAGPR;
-  assert(&RBAGPR == &AMDGPU::AGPRRegBank);
+  assert(&getRegBank(AMDGPU::SGPRRegBankID) == &AMDGPU::SGPRRegBank &&
+         &getRegBank(AMDGPU::VGPRRegBankID) == &AMDGPU::VGPRRegBank &&
+         &getRegBank(AMDGPU::AGPRRegBankID) == &AMDGPU::AGPRRegBank);
 }
 
 static bool isVectorRegisterBank(const RegisterBank &Bank) {