From: Jakub Jelinek <jakub@redhat.com>
Date: Tue, 26 Apr 2022 08:11:58 +0000 (+0200)
Subject: ifcvt: Improve noce_try_store_flag_mask [PR105314]
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=7d31c678d68d7b6820a958584619ca763b0eb9c5;p=test_jj.git

ifcvt: Improve noce_try_store_flag_mask [PR105314]

The following testcase regressed on riscv due to the splitting of critical
edges in the sink pass, similarly to x86_64 compared to GCC 11 we now swap
the edges, whether true or false edge goes to an empty forwarded bb.
From GIMPLE POV, those 2 forms are equivalent, but as can be seen here, for
some ifcvt opts it matters one way or another.

On this testcase, noce_try_store_flag_mask used to trigger and transformed
if (pseudo2) pseudo1 = 0;
into
pseudo1 &= -(pseudo2 == 0);
But with the swapped edges ifcvt actually sees
if (!pseudo2) pseudo3 = pseudo1; else pseudo3 = 0;
and noce_try_store_flag_mask punts.  IMHO there is no reason why it
should punt those, it is equivalent to
pseudo3 = pseudo1 & -(pseudo2 == 0);
and especially if the target has 3 operand AND, it shouldn't be any more
costly (and even with 2 operand AND, it might very well happen that RA
can make it happen without any extra moves).

Initially I've just removed the rtx_equal_p calls from the conditions
and didn't add anything there, but that broke aarch64 bootstrap and
regressed some testcases on x86_64, where if_info->a or if_info->b could be
some larger expression that we can't force into a register.
Furthermore, the case where both if_info->a and if_info->b are constants is
better handled by other ifcvt optimizations like noce_try_store_flag
or noce_try_inverse_constants or noce_try_store_flag_constants.
So, I've restricted it to just a REG (perhaps SUBREG of REG might be ok too)
next to what has been handled previously.

2022-04-26  Jakub Jelinek  <jakub@redhat.com>

	PR rtl-optimization/105314
	* ifcvt.cc (noce_try_store_flag_mask): Don't require that the non-zero
	operand is equal to if_info->x, instead use the non-zero operand
	as one of the operands of AND with if_info->x as target.

	* gcc.target/riscv/pr105314.c: New test.
---

diff --git a/gcc/ifcvt.cc b/gcc/ifcvt.cc
index 22960a6..b983e87 100644
--- a/gcc/ifcvt.cc
+++ b/gcc/ifcvt.cc
@@ -1678,10 +1678,10 @@ noce_try_store_flag_mask (struct noce_if_info *if_info)
   reversep = 0;
 
   if ((if_info->a == const0_rtx
-       && rtx_equal_p (if_info->b, if_info->x))
+       && (REG_P (if_info->b) || rtx_equal_p (if_info->b, if_info->x)))
       || ((reversep = (noce_reversed_cond_code (if_info) != UNKNOWN))
 	  && if_info->b == const0_rtx
-	  && rtx_equal_p (if_info->a, if_info->x)))
+	  && (REG_P (if_info->a) || rtx_equal_p (if_info->a, if_info->x))))
     {
       start_sequence ();
       target = noce_emit_store_flag (if_info,
@@ -1689,7 +1689,7 @@ noce_try_store_flag_mask (struct noce_if_info *if_info)
 				     reversep, -1);
       if (target)
         target = expand_simple_binop (GET_MODE (if_info->x), AND,
-				      if_info->x,
+				      reversep ? if_info->a : if_info->b,
 				      target, if_info->x, 0,
 				      OPTAB_WIDEN);
 
diff --git a/gcc/testsuite/gcc.target/riscv/pr105314.c b/gcc/testsuite/gcc.target/riscv/pr105314.c
new file mode 100644
index 0000000..7a54577
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/pr105314.c
@@ -0,0 +1,12 @@
+/* PR rtl-optimization/105314 */
+/* { dg-do compile } *
+/* { dg-options "-O2" } */
+/* { dg-final { scan-assembler-not "\tbeq\t" } } */
+
+long
+foo (long a, long b, long c)
+{
+  if (c)
+    a = 0;
+  return a;
+}