From: Michal Simek <michal.simek@xilinx.com>
Date: Wed, 26 Feb 2020 10:11:38 +0000 (+0100)
Subject: ARM: zynq: Do not include full zynq-7000.dtsi to cse-nor configuration
X-Git-Tag: v2020.10~292^2~4^2~26
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=7c49a6d08e6dbdcb004f9a1129b40b297a2ac2f2;p=platform%2Fkernel%2Fu-boot.git

ARM: zynq: Do not include full zynq-7000.dtsi to cse-nor configuration

There is no real need to include full DT when only some nodes are enough to
use. It will save some space.

Retested with FSBL for initial SoC setup. SPL didn't work.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---

diff --git a/arch/arm/dts/zynq-cse-nor.dts b/arch/arm/dts/zynq-cse-nor.dts
index 9710aba..4030851 100644
--- a/arch/arm/dts/zynq-cse-nor.dts
+++ b/arch/arm/dts/zynq-cse-nor.dts
@@ -5,7 +5,6 @@
  * Copyright (C) 2018 Xilinx, Inc.
  */
 /dts-v1/;
-#include "zynq-7000.dtsi"
 
 / {
 	#address-cells = <1>;
@@ -33,27 +32,21 @@
 	};
 
 	amba: amba {
+		u-boot,dm-pre-reloc;
 		compatible = "simple-bus";
 		#address-cells = <1>;
 		#size-cells = <1>;
-		interrupt-parent = <&intc>;
 		ranges;
 
-		intc: interrupt-controller@f8f01000 {
-			compatible = "arm,cortex-a9-gic";
-			#interrupt-cells = <3>;
-			interrupt-controller;
-			reg = <0xF8F01000 0x1000>,
-			      <0xF8F00100 0x100>;
-		};
-
 		slcr: slcr@f8000000 {
+			u-boot,dm-pre-reloc;
 			#address-cells = <1>;
 			#size-cells = <1>;
 			compatible = "xlnx,zynq-slcr", "syscon", "simple-bus";
 			reg = <0xF8000000 0x1000>;
 			ranges;
 			clkc: clkc@100 {
+				u-boot,dm-pre-reloc;
 				#clock-cells = <1>;
 				compatible = "xlnx,ps7-clkc";
 				clock-output-names = "armpll", "ddrpll",