From: Thong Thai Date: Thu, 12 Mar 2020 14:05:48 +0000 (-0400) Subject: radeon: Pass HEVC encode crop parameters to the encoder X-Git-Tag: upstream/21.0.0~5223 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=7b9414f23f3d74bf460b3e3ff82055f644bd1aed;p=platform%2Fupstream%2Fmesa.git radeon: Pass HEVC encode crop parameters to the encoder Signed-off-by: Thong Thai Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2351 Reviewed-by: Leo Liu Part-of: --- diff --git a/src/gallium/drivers/radeon/radeon_uvd_enc.c b/src/gallium/drivers/radeon/radeon_uvd_enc.c index 4ac4515..82aebc4 100644 --- a/src/gallium/drivers/radeon/radeon_uvd_enc.c +++ b/src/gallium/drivers/radeon/radeon_uvd_enc.c @@ -60,10 +60,19 @@ static void radeon_uvd_enc_get_param(struct radeon_uvd_encoder *enc, enc->enc_pic.not_referenced = pic->not_referenced; enc->enc_pic.is_iframe = (pic->picture_type == PIPE_H265_ENC_PICTURE_TYPE_IDR) || (pic->picture_type == PIPE_H265_ENC_PICTURE_TYPE_I); - enc->enc_pic.crop_left = 0; - enc->enc_pic.crop_right = (align(enc->base.width, 16) - enc->base.width) / 2; - enc->enc_pic.crop_top = 0; - enc->enc_pic.crop_bottom = (align(enc->base.height, 16) - enc->base.height) / 2; + + if (pic->seq.conformance_window_flag) { + enc->enc_pic.crop_left = pic->seq.conf_win_left_offset; + enc->enc_pic.crop_right = pic->seq.conf_win_right_offset; + enc->enc_pic.crop_top = pic->seq.conf_win_top_offset; + enc->enc_pic.crop_bottom = pic->seq.conf_win_bottom_offset; + } else { + enc->enc_pic.crop_left = 0; + enc->enc_pic.crop_right = (align(enc->base.width, 16) - enc->base.width) / 2; + enc->enc_pic.crop_top = 0; + enc->enc_pic.crop_bottom = (align(enc->base.height, 16) - enc->base.height) / 2; + } + enc->enc_pic.general_tier_flag = pic->seq.general_tier_flag; enc->enc_pic.general_profile_idc = pic->seq.general_profile_idc; enc->enc_pic.general_level_idc = pic->seq.general_level_idc; diff --git a/src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c b/src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c index 029f3a6..b6e02e5 100644 --- a/src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c +++ b/src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c @@ -429,6 +429,7 @@ static void radeon_uvd_enc_nalu_sps_hevc(struct radeon_uvd_encoder *enc) ? 0x1 : 0x0; radeon_uvd_enc_code_fixed_bits(enc, conformance_window_flag, 1); + if (conformance_window_flag == 1) { radeon_uvd_enc_code_ue(enc, enc->enc_pic.crop_left); radeon_uvd_enc_code_ue(enc, enc->enc_pic.crop_right); diff --git a/src/gallium/drivers/radeon/radeon_vcn_enc.c b/src/gallium/drivers/radeon/radeon_vcn_enc.c index 9b7403d..331724e 100644 --- a/src/gallium/drivers/radeon/radeon_vcn_enc.c +++ b/src/gallium/drivers/radeon/radeon_vcn_enc.c @@ -106,10 +106,19 @@ static void radeon_vcn_enc_get_param(struct radeon_encoder *enc, struct pipe_pic enc->enc_pic.not_referenced = pic->not_referenced; enc->enc_pic.is_idr = (pic->picture_type == PIPE_H265_ENC_PICTURE_TYPE_IDR) || (pic->picture_type == PIPE_H265_ENC_PICTURE_TYPE_I); - enc->enc_pic.crop_left = 0; - enc->enc_pic.crop_right = (align(enc->base.width, 16) - enc->base.width) / 2; - enc->enc_pic.crop_top = 0; - enc->enc_pic.crop_bottom = (align(enc->base.height, 16) - enc->base.height) / 2; + + if (pic->seq.conformance_window_flag) { + enc->enc_pic.crop_left = pic->seq.conf_win_left_offset; + enc->enc_pic.crop_right = pic->seq.conf_win_right_offset; + enc->enc_pic.crop_top = pic->seq.conf_win_top_offset; + enc->enc_pic.crop_bottom = pic->seq.conf_win_bottom_offset; + } else { + enc->enc_pic.crop_left = 0; + enc->enc_pic.crop_right = (align(enc->base.width, 16) - enc->base.width) / 2; + enc->enc_pic.crop_top = 0; + enc->enc_pic.crop_bottom = (align(enc->base.height, 16) - enc->base.height) / 2; + } + enc->enc_pic.general_tier_flag = pic->seq.general_tier_flag; enc->enc_pic.general_profile_idc = pic->seq.general_profile_idc; enc->enc_pic.general_level_idc = pic->seq.general_level_idc; diff --git a/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c b/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c index 66b4578..b82f434 100644 --- a/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c +++ b/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c @@ -396,7 +396,17 @@ static void radeon_enc_nalu_sps_hevc(struct radeon_encoder *enc) radeon_enc_code_ue(enc, enc->enc_pic.chroma_format_idc); radeon_enc_code_ue(enc, enc->enc_pic.session_init.aligned_picture_width); radeon_enc_code_ue(enc, enc->enc_pic.session_init.aligned_picture_height); - radeon_enc_code_fixed_bits(enc, 0x0, 1); + + if ((enc->enc_pic.crop_left != 0) || (enc->enc_pic.crop_right != 0) || + (enc->enc_pic.crop_top != 0) || (enc->enc_pic.crop_bottom != 0)) { + radeon_enc_code_fixed_bits(enc, 0x1, 1); + radeon_enc_code_ue(enc, enc->enc_pic.crop_left); + radeon_enc_code_ue(enc, enc->enc_pic.crop_right); + radeon_enc_code_ue(enc, enc->enc_pic.crop_top); + radeon_enc_code_ue(enc, enc->enc_pic.crop_bottom); + } else + radeon_enc_code_fixed_bits(enc, 0x0, 1); + radeon_enc_code_ue(enc, enc->enc_pic.bit_depth_luma_minus8); radeon_enc_code_ue(enc, enc->enc_pic.bit_depth_chroma_minus8); radeon_enc_code_ue(enc, enc->enc_pic.log2_max_poc - 4); diff --git a/src/gallium/drivers/radeon/radeon_vcn_enc_2_0.c b/src/gallium/drivers/radeon/radeon_vcn_enc_2_0.c index 52a6ee7..56c6bf9 100644 --- a/src/gallium/drivers/radeon/radeon_vcn_enc_2_0.c +++ b/src/gallium/drivers/radeon/radeon_vcn_enc_2_0.c @@ -137,7 +137,17 @@ static void radeon_enc_nalu_sps_hevc(struct radeon_encoder *enc) radeon_enc_code_ue(enc, enc->enc_pic.chroma_format_idc); radeon_enc_code_ue(enc, enc->enc_pic.session_init.aligned_picture_width); radeon_enc_code_ue(enc, enc->enc_pic.session_init.aligned_picture_height); - radeon_enc_code_fixed_bits(enc, 0x0, 1); + + if ((enc->enc_pic.crop_left != 0) || (enc->enc_pic.crop_right != 0) || + (enc->enc_pic.crop_top != 0) || (enc->enc_pic.crop_bottom != 0)) { + radeon_enc_code_fixed_bits(enc, 0x1, 1); + radeon_enc_code_ue(enc, enc->enc_pic.crop_left); + radeon_enc_code_ue(enc, enc->enc_pic.crop_right); + radeon_enc_code_ue(enc, enc->enc_pic.crop_top); + radeon_enc_code_ue(enc, enc->enc_pic.crop_bottom); + } else + radeon_enc_code_fixed_bits(enc, 0x0, 1); + radeon_enc_code_ue(enc, enc->enc_pic.bit_depth_luma_minus8); radeon_enc_code_ue(enc, enc->enc_pic.bit_depth_chroma_minus8); radeon_enc_code_ue(enc, enc->enc_pic.log2_max_poc - 4);