From: Matt Arsenault <Matthew.Arsenault@amd.com>
Date: Fri, 9 Dec 2016 17:57:43 +0000 (+0000)
Subject: AMDGPU: Fix isTypeDesirableForOp for i16
X-Git-Tag: llvmorg-4.0.0-rc1~2494
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=7b00cf4706f7dd855096ef20313617fd89323337;p=platform%2Fupstream%2Fllvm.git

AMDGPU: Fix isTypeDesirableForOp for i16

This should do nothing for targets without i16.

llvm-svn: 289235
---

diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index eeab482..0c35c27 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -658,10 +658,22 @@ bool SITargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
 }
 
 bool SITargetLowering::isTypeDesirableForOp(unsigned Op, EVT VT) const {
-
-  // i16 is not desirable unless it is a load or a store.
-  if (VT == MVT::i16 && Op != ISD::LOAD && Op != ISD::STORE)
-    return false;
+  if (Subtarget->has16BitInsts() && VT == MVT::i16) {
+    switch (Op) {
+    case ISD::LOAD:
+    case ISD::STORE:
+
+    // These operations are done with 32-bit instructions anyway.
+    case ISD::AND:
+    case ISD::OR:
+    case ISD::XOR:
+    case ISD::SELECT:
+      // TODO: Extensions?
+      return true;
+    default:
+      return false;
+    }
+  }
 
   // SimplifySetCC uses this function to determine whether or not it should
   // create setcc with i1 operands.  We don't have instructions for i1 setcc.