From: Jack Carter Date: Sat, 19 Jan 2013 02:00:40 +0000 (+0000) Subject: This is a resubmittal. For some reason it broke the bots yesterday X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=7ab15fafe3e28557cc0688c85cbbc3f7e86d3456;p=platform%2Fupstream%2Fllvm.git This is a resubmittal. For some reason it broke the bots yesterday but I cannot reproduce the problem and have scrubed my sources and even tested with llvm-lit -v --vg. Formatting fixes. Mostly long lines and blank spaces at end of lines. Contributer: Jack Carter llvm-svn: 172882 --- diff --git a/llvm/lib/Target/Mips/Disassembler/LLVMBuild.txt b/llvm/lib/Target/Mips/Disassembler/LLVMBuild.txt index 048ad0d..7101c06 100644 --- a/llvm/lib/Target/Mips/Disassembler/LLVMBuild.txt +++ b/llvm/lib/Target/Mips/Disassembler/LLVMBuild.txt @@ -1,4 +1,4 @@ -;===- ./lib/Target/Mips/Disassembler/LLVMBuild.txt --------------*- Conf -*--===; +;===- ./lib/Target/Mips/Disassembler/LLVMBuild.txt -------------*- Conf -*--===; ; ; The LLVM Compiler Infrastructure ; diff --git a/llvm/lib/Target/Mips/Disassembler/Makefile b/llvm/lib/Target/Mips/Disassembler/Makefile index a78feba..7900373 100644 --- a/llvm/lib/Target/Mips/Disassembler/Makefile +++ b/llvm/lib/Target/Mips/Disassembler/Makefile @@ -1,4 +1,4 @@ -##===- lib/Target/Mips/Disassembler/Makefile ----------------*- Makefile -*-===## +##===- lib/Target/Mips/Disassembler/Makefile ---------------*- Makefile -*-===## # # The LLVM Compiler Infrastructure # diff --git a/llvm/lib/Target/Mips/Mips16InstrInfo.cpp b/llvm/lib/Target/Mips/Mips16InstrInfo.cpp index 91b5ba0..117faea 100644 --- a/llvm/lib/Target/Mips/Mips16InstrInfo.cpp +++ b/llvm/lib/Target/Mips/Mips16InstrInfo.cpp @@ -28,7 +28,8 @@ using namespace llvm; static cl::opt NeverUseSaveRestore( "mips16-never-use-save-restore", cl::init(false), - cl::desc("For testing ability to adjust stack pointer without save/restore instruction"), + cl::desc("For testing ability to adjust stack pointer " + "without save/restore instruction"), cl::Hidden); @@ -169,15 +170,16 @@ unsigned Mips16InstrInfo::GetOppositeBranchOpc(unsigned Opc) const { } // Adjust SP by FrameSize bytes. Save RA, S0, S1 -void Mips16InstrInfo::makeFrame(unsigned SP, int64_t FrameSize, MachineBasicBlock &MBB, +void Mips16InstrInfo::makeFrame(unsigned SP, int64_t FrameSize, + MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const { DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc(); if (!NeverUseSaveRestore) { if (isUInt<11>(FrameSize)) BuildMI(MBB, I, DL, get(Mips::SaveRaF16)).addImm(FrameSize); else { - int Base = 2040; // should create template function like isUInt that returns largest - // possible n bit unsigned integer + int Base = 2040; // should create template function like isUInt that + // returns largest possible n bit unsigned integer int64_t Remainder = FrameSize - Base; BuildMI(MBB, I, DL, get(Mips::SaveRaF16)). addImm(Base); if (isInt<16>(-Remainder)) @@ -193,13 +195,16 @@ void Mips16InstrInfo::makeFrame(unsigned SP, int64_t FrameSize, MachineBasicBloc // sw s1, -8[sp] // sw s0, -12[sp] - MachineInstrBuilder MIB1 = BuildMI(MBB, I, DL, get(Mips::SwRxSpImmX16), Mips::RA); + MachineInstrBuilder MIB1 = BuildMI(MBB, I, DL, get(Mips::SwRxSpImmX16), + Mips::RA); MIB1.addReg(Mips::SP); MIB1.addImm(-4); - MachineInstrBuilder MIB2 = BuildMI(MBB, I, DL, get(Mips::SwRxSpImmX16), Mips::S1); + MachineInstrBuilder MIB2 = BuildMI(MBB, I, DL, get(Mips::SwRxSpImmX16), + Mips::S1); MIB2.addReg(Mips::SP); MIB2.addImm(-8); - MachineInstrBuilder MIB3 = BuildMI(MBB, I, DL, get(Mips::SwRxSpImmX16), Mips::S0); + MachineInstrBuilder MIB3 = BuildMI(MBB, I, DL, get(Mips::SwRxSpImmX16), + Mips::S0); MIB3.addReg(Mips::SP); MIB3.addImm(-12); adjustStackPtrBig(SP, -FrameSize, MBB, I, Mips::V0, Mips::V1); @@ -207,15 +212,16 @@ void Mips16InstrInfo::makeFrame(unsigned SP, int64_t FrameSize, MachineBasicBloc } // Adjust SP by FrameSize bytes. Restore RA, S0, S1 -void Mips16InstrInfo::restoreFrame(unsigned SP, int64_t FrameSize, MachineBasicBlock &MBB, - MachineBasicBlock::iterator I) const { +void Mips16InstrInfo::restoreFrame(unsigned SP, int64_t FrameSize, + MachineBasicBlock &MBB, + MachineBasicBlock::iterator I) const { DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc(); if (!NeverUseSaveRestore) { if (isUInt<11>(FrameSize)) BuildMI(MBB, I, DL, get(Mips::RestoreRaF16)).addImm(FrameSize); else { - int Base = 2040; // should create template function like isUInt that returns largest - // possible n bit unsigned integer + int Base = 2040; // should create template function like isUInt that + // returns largest possible n bit unsigned integer int64_t Remainder = FrameSize - Base; if (isInt<16>(Remainder)) BuildMI(MBB, I, DL, get(Mips::AddiuSpImmX16)). addImm(Remainder); @@ -229,15 +235,19 @@ void Mips16InstrInfo::restoreFrame(unsigned SP, int64_t FrameSize, MachineBasicB // lw ra, -4[sp] // lw s1, -8[sp] // lw s0, -12[sp] - MachineInstrBuilder MIB1 = BuildMI(MBB, I, DL, get(Mips::LwRxSpImmX16), Mips::A0); + MachineInstrBuilder MIB1 = BuildMI(MBB, I, DL, get(Mips::LwRxSpImmX16), + Mips::A0); MIB1.addReg(Mips::SP); MIB1.addImm(-4); - MachineInstrBuilder MIB0 = BuildMI(MBB, I, DL, get(Mips::Move32R16), Mips::RA); + MachineInstrBuilder MIB0 = BuildMI(MBB, I, DL, get(Mips::Move32R16), + Mips::RA); MIB0.addReg(Mips::A0); - MachineInstrBuilder MIB2 = BuildMI(MBB, I, DL, get(Mips::LwRxSpImmX16), Mips::S1); + MachineInstrBuilder MIB2 = BuildMI(MBB, I, DL, get(Mips::LwRxSpImmX16), + Mips::S1); MIB2.addReg(Mips::SP); MIB2.addImm(-8); - MachineInstrBuilder MIB3 = BuildMI(MBB, I, DL, get(Mips::LwRxSpImmX16), Mips::S0); + MachineInstrBuilder MIB3 = BuildMI(MBB, I, DL, get(Mips::LwRxSpImmX16), + Mips::S0); MIB3.addReg(Mips::SP); MIB3.addImm(-12); } @@ -245,10 +255,12 @@ void Mips16InstrInfo::restoreFrame(unsigned SP, int64_t FrameSize, MachineBasicB } // Adjust SP by Amount bytes where bytes can be up to 32bit number. -// This can only be called at times that we know that there is at least one free register. +// This can only be called at times that we know that there is at least one free +// register. // This is clearly safe at prologue and epilogue. // -void Mips16InstrInfo::adjustStackPtrBig(unsigned SP, int64_t Amount, MachineBasicBlock &MBB, +void Mips16InstrInfo::adjustStackPtrBig(unsigned SP, int64_t Amount, + MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned Reg1, unsigned Reg2) const { DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc(); @@ -269,11 +281,13 @@ void Mips16InstrInfo::adjustStackPtrBig(unsigned SP, int64_t Amount, MachineBasi MachineInstrBuilder MIB3 = BuildMI(MBB, I, DL, get(Mips::AdduRxRyRz16), Reg1); MIB3.addReg(Reg1); MIB3.addReg(Reg2, RegState::Kill); - MachineInstrBuilder MIB4 = BuildMI(MBB, I, DL, get(Mips::Move32R16), Mips::SP); + MachineInstrBuilder MIB4 = BuildMI(MBB, I, DL, get(Mips::Move32R16), + Mips::SP); MIB4.addReg(Reg1, RegState::Kill); } -void Mips16InstrInfo::adjustStackPtrBigUnrestricted(unsigned SP, int64_t Amount, MachineBasicBlock &MBB, +void Mips16InstrInfo::adjustStackPtrBigUnrestricted(unsigned SP, int64_t Amount, + MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const { assert(false && "adjust stack pointer amount exceeded"); } diff --git a/llvm/lib/Target/Mips/Mips16InstrInfo.td b/llvm/lib/Target/Mips/Mips16InstrInfo.td index e8e2f3c..56553d9 100644 --- a/llvm/lib/Target/Mips/Mips16InstrInfo.td +++ b/llvm/lib/Target/Mips/Mips16InstrInfo.td @@ -257,7 +257,7 @@ class FRR16_JALRC_RA_only_ins nd_, bits<1> l_, class FRR16_JALRC_ins nd, bits<1> l, bits<1> ra, string asmstr, InstrItinClass itin>: - FRR16_JALRC ; // @@ -363,7 +363,7 @@ def imm32: Operand; def Constant32: MipsPseudo16<(outs), (ins imm32:$imm), "\t.word $imm", []>; - + def LwConstant32: MipsPseudo16<(outs), (ins CPU16Regs:$rx, imm32:$imm), "lw\t$rx, 1f\n\tb\t2f\n\t.align\t2\n1: \t.word\t$imm\n2:", []>; @@ -430,7 +430,7 @@ def AddiuSpImmX16 : FEXT_I816_SP_ins<0b011, "addiu", IIAlu> { let Defs = [SP]; let Uses = [SP]; -} +} // // Format: ADDU rz, rx, ry MIPS16e @@ -1072,8 +1072,8 @@ class UncondBranch16_pat: // Indirect branch def: Mips16Pat< - (brind CPU16Regs:$rs), - (JrcRx16 CPU16Regs:$rs)>; + (brind CPU16Regs:$rs), + (JrcRx16 CPU16Regs:$rs)>; // Jump and Link (Call) @@ -1562,7 +1562,7 @@ def: Mips16Pat<(add CPU16Regs:$hi, (MipsLo tglobaladdr:$lo)), // hi/lo relocs -def : Mips16Pat<(MipsHi tglobaltlsaddr:$in), +def : Mips16Pat<(MipsHi tglobaltlsaddr:$in), (SllX16 (LiRxImmX16 tglobaltlsaddr:$in), 16)>; // wrapper_pic diff --git a/llvm/lib/Target/Mips/MipsInstrInfo.td b/llvm/lib/Target/Mips/MipsInstrInfo.td index 9085a26..74f3178 100644 --- a/llvm/lib/Target/Mips/MipsInstrInfo.td +++ b/llvm/lib/Target/Mips/MipsInstrInfo.td @@ -951,10 +951,14 @@ def : InstAlias<"slt $rs, $rt, $imm", def : InstAlias<"xor $rs, $rt, $imm", (XORi CPURegsOpnd:$rs, CPURegsOpnd:$rt, simm16:$imm)>, Requires<[NotMips64]>; -def : InstAlias<"mfc0 $rt, $rd", (MFC0_3OP CPURegsOpnd:$rt, CPURegsOpnd:$rd, 0)>; -def : InstAlias<"mtc0 $rt, $rd", (MTC0_3OP CPURegsOpnd:$rd, 0, CPURegsOpnd:$rt)>; -def : InstAlias<"mfc2 $rt, $rd", (MFC2_3OP CPURegsOpnd:$rt, CPURegsOpnd:$rd, 0)>; -def : InstAlias<"mtc2 $rt, $rd", (MTC2_3OP CPURegsOpnd:$rd, 0, CPURegsOpnd:$rt)>; +def : InstAlias<"mfc0 $rt, $rd", (MFC0_3OP CPURegsOpnd:$rt, + CPURegsOpnd:$rd, 0)>; +def : InstAlias<"mtc0 $rt, $rd", (MTC0_3OP CPURegsOpnd:$rd, 0, + CPURegsOpnd:$rt)>; +def : InstAlias<"mfc2 $rt, $rd", (MFC2_3OP CPURegsOpnd:$rt, + CPURegsOpnd:$rd, 0)>; +def : InstAlias<"mtc2 $rt, $rd", (MTC2_3OP CPURegsOpnd:$rd, 0, + CPURegsOpnd:$rt)>; //===----------------------------------------------------------------------===// // Assembler Pseudo Instructions diff --git a/llvm/lib/Target/Mips/MipsLongBranch.cpp b/llvm/lib/Target/Mips/MipsLongBranch.cpp index 30f68b1..2efe534 100644 --- a/llvm/lib/Target/Mips/MipsLongBranch.cpp +++ b/llvm/lib/Target/Mips/MipsLongBranch.cpp @@ -10,10 +10,10 @@ // This pass expands a branch or jump instruction into a long branch if its // offset is too large to fit into its immediate field. // -// FIXME: -// 1. Fix pc-region jump instructions which cross 256MB segment boundaries. +// FIXME: +// 1. Fix pc-region jump instructions which cross 256MB segment boundaries. // 2. If program has inline assembly statements whose size cannot be -// determined accurately, load branch target addresses from the GOT. +// determined accurately, load branch target addresses from the GOT. //===----------------------------------------------------------------------===// #define DEBUG_TYPE "mips-long-branch"