From: Simon Moll <simon.moll@emea.nec.com>
Date: Fri, 30 Apr 2021 13:46:59 +0000 (+0200)
Subject: [VE] VP intrinsics are legal
X-Git-Tag: llvmorg-14-init~7970
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=7a8664561116cd3c1ce2e66826c479649ae741b9;p=platform%2Fupstream%2Fllvm.git

[VE] VP intrinsics are legal
---

diff --git a/llvm/lib/Target/VE/VETargetTransformInfo.h b/llvm/lib/Target/VE/VETargetTransformInfo.h
index 6730c43..6e6f4d2 100644
--- a/llvm/lib/Target/VE/VETargetTransformInfo.h
+++ b/llvm/lib/Target/VE/VETargetTransformInfo.h
@@ -64,6 +64,14 @@ public:
     llvm_unreachable("Unsupported register kind");
   }
 
+  /// \returns How the target needs this vector-predicated operation to be
+  /// transformed.
+  TargetTransformInfo::VPLegalization
+  getVPLegalizationStrategy(const VPIntrinsic &PI) const {
+    using VPLegalization = TargetTransformInfo::VPLegalization;
+    return VPLegalization(VPLegalization::Legal, VPLegalization::Legal);
+  }
+
   unsigned getMinVectorRegisterBitWidth() const {
     // TODO report vregs once vector isel is stable.
     return 0;