From: Marek Olšák <marek.olsak@amd.com>
Date: Tue, 16 Jul 2019 23:04:48 +0000 (-0400)
Subject: radeonsi: fix compute-based culling regression in 1ce52c1e373
X-Git-Tag: upstream/19.3.0~3941
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=7a764b963a50cfab4a684b492c377d31a669d747;p=platform%2Fupstream%2Fmesa.git

radeonsi: fix compute-based culling regression in 1ce52c1e373

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
---

diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c
index f39b7c6..a099805 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -759,7 +759,7 @@ static void si_emit_draw_registers(struct si_context *sctx,
 				   bool primitive_restart)
 {
 	struct radeon_cmdbuf *cs = sctx->gfx_cs;
-	unsigned vgt_prim = si_conv_pipe_prim(info->mode);
+	unsigned vgt_prim = si_conv_pipe_prim(prim);
 
 	if (sctx->chip_class >= GFX10)
 		gfx10_emit_ge_cntl(sctx, num_patches);