From: Lukasz Luba Date: Tue, 15 Jan 2019 17:54:26 +0000 (+0100) Subject: clk: samsung: add new CLK_MOUT_WCORE for NoC in Exynos5420 SoC X-Git-Tag: submit/tizen/20190329.020226~127 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=79dcbb41580eab8e4404e6b2dcaa6b172ca354a3;p=platform%2Fkernel%2Flinux-exynos.git clk: samsung: add new CLK_MOUT_WCORE for NoC in Exynos5420 SoC New clock ID (CLK_MOUT_WCORE) is needed for changing parent of the main NoC bus clock. Change-Id: I21dbd629d0f4529f94ca0c07982cddcef63f7cc4 Signed-off-by: Lukasz Luba --- diff --git a/include/dt-bindings/clock/exynos5420.h b/include/dt-bindings/clock/exynos5420.h index 0484781ff996..7695c7417d10 100644 --- a/include/dt-bindings/clock/exynos5420.h +++ b/include/dt-bindings/clock/exynos5420.h @@ -235,6 +235,7 @@ #define CLK_MOUT_ACLK_G3D 661 #define CLK_MOUT_SCLK_SPLL 662 #define CLK_MOUT_MX_MSPLL_CCORE_PHY 663 +#define CLK_MOUT_WCORE 664 /* divider clocks */ #define CLK_DOUT_PIXEL 768