From: Simon Pilgrim <llvm-dev@redking.me.uk>
Date: Mon, 17 Aug 2020 11:46:31 +0000 (+0100)
Subject: [DemandedBits] Reorder addition test checks. NFC.
X-Git-Tag: llvmorg-13-init~14556
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=79d9e2cd93a3ff7b448f40caf50dbfd3516f7c0d;p=platform%2Fupstream%2Fllvm.git

[DemandedBits] Reorder addition test checks. NFC.

As suggested on D72423 we should try to keep the same order as the original IR
---

diff --git a/llvm/test/Analysis/DemandedBits/add.ll b/llvm/test/Analysis/DemandedBits/add.ll
index 102d667..9203ed1 100644
--- a/llvm/test/Analysis/DemandedBits/add.ll
+++ b/llvm/test/Analysis/DemandedBits/add.ll
@@ -1,14 +1,14 @@
 ; RUN: opt -S -demanded-bits -analyze < %s | FileCheck %s
 ; RUN: opt -S -disable-output -passes="print<demanded-bits>" < %s 2>&1 | FileCheck %s
 
-; CHECK-DAG: DemandedBits: 0x1f for   %5 = or i32 %2, %3
-; CHECK-DAG: DemandedBits: 0xffffffff for   %8 = and i32 %7, 16
-; CHECK-DAG: DemandedBits: 0x1f for   %4 = and i32 %d, 4
 ; CHECK-DAG: DemandedBits: 0x1f for   %1 = and i32 %a, 9
+; CHECK-DAG: DemandedBits: 0x1f for   %2 = and i32 %b, 9
 ; CHECK-DAG: DemandedBits: 0x1f for   %3 = and i32 %c, 13
-; CHECK-DAG: DemandedBits: 0x10 for   %7 = add i32 %1, %6
+; CHECK-DAG: DemandedBits: 0x1f for   %4 = and i32 %d, 4
+; CHECK-DAG: DemandedBits: 0x1f for   %5 = or i32 %2, %3
 ; CHECK-DAG: DemandedBits: 0x1f for   %6 = or i32 %4, %5
-; CHECK-DAG: DemandedBits: 0x1f for   %2 = and i32 %b, 9
+; CHECK-DAG: DemandedBits: 0x10 for   %7 = add i32 %1, %6
+; CHECK-DAG: DemandedBits: 0xffffffff for   %8 = and i32 %7, 16
 define i32 @test_add(i32 %a, i32 %b, i32 %c, i32 %d) {
   %1 = and i32 %a, 9
   %2 = and i32 %b, 9