From: Ville Syrjälä Date: Fri, 21 Apr 2017 18:14:30 +0000 (+0300) Subject: drm/i915: Enable HPLL watermarks on g4x X-Git-Tag: v4.14-rc1~484^2~32^2~96 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=79d94306ea7a07189222cfa7a454bc04480e5c50;p=platform%2Fkernel%2Flinux-rpi.git drm/i915: Enable HPLL watermarks on g4x I don't see why we couldn't use the HPLL watermarks on g4x. So let's enable them. Let's assume a 35 usec memory latency for the HPLL mode. That's roughly what PNV uses. Based on the behaviour of the ELK box I have 35 usec is probably overkill. Actually all the current latency values used seem overkill as I can reduce them pretty drastically before I start to see underruns. But let's play things a bit safe for now. Signed-off-by: Ville Syrjälä Link: http://patchwork.freedesktop.org/patch/msgid/20170421181432.15216-14-ville.syrjala@linux.intel.com Reviewed-by: Maarten Lankhorst --- diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 9b0a6a4..957ef10 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -1020,8 +1020,9 @@ static void g4x_setup_wm_latency(struct drm_i915_private *dev_priv) /* all latencies in usec */ dev_priv->wm.pri_latency[G4X_WM_LEVEL_NORMAL] = 5; dev_priv->wm.pri_latency[G4X_WM_LEVEL_SR] = 12; + dev_priv->wm.pri_latency[G4X_WM_LEVEL_HPLL] = 35; - dev_priv->wm.max_level = G4X_WM_LEVEL_SR; + dev_priv->wm.max_level = G4X_WM_LEVEL_HPLL; } static int g4x_plane_fifo_size(enum plane_id plane_id, int level)