From: Roman Lebedev Date: Tue, 5 Oct 2021 13:28:04 +0000 (+0300) Subject: [X86][Costmodel] Load/store i32/f32 Stride=6 VF=16 interleaving costs X-Git-Tag: upstream/15.0.7~29591 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=79d6d12d9585dd584f259fa7395ad9465bef9aeb;p=platform%2Fupstream%2Fllvm.git [X86][Costmodel] Load/store i32/f32 Stride=6 VF=16 interleaving costs This one required quite a bit of an assembly surgery, but i think it's in the right ballpark.. The only sched models that for cpu's that support avx2 but not avx512 are: haswell, broadwell, skylake, zen1-3 For load we have: https://godbolt.org/z/na97Kb96o - for intels `Block RThroughput: <=64.0`; for ryzens, `Block RThroughput: <=32.0` So could pick cost of `64`. For store we have: https://godbolt.org/z/GG1WeoKar - for intels `Block RThroughput: =66.0`; for ryzens, `Block RThroughput: <=27.5` So we could pick cost of `66`. I'm directly using the shuffling asm the llc produced, without any manual fixups that may be needed to ensure sequential execution. Reviewed By: RKSimon Differential Revision: https://reviews.llvm.org/D111091 --- diff --git a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp index 2099c92..0128f23 100644 --- a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp +++ b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp @@ -5151,6 +5151,7 @@ InstructionCost X86TTIImpl::getInterleavedMemoryOpCostAVX2( {6, MVT::v2i32, 6}, // (load 12i32 and) deinterleave into 6 x 2i32 {6, MVT::v4i32, 15}, // (load 24i32 and) deinterleave into 6 x 4i32 {6, MVT::v8i32, 31}, // (load 48i32 and) deinterleave into 6 x 8i32 + {6, MVT::v16i32, 64}, // (load 96i32 and) deinterleave into 6 x 16i32 {8, MVT::v8i32, 40} // (load 64i32 and) deinterleave into 8 x 8i32 }; @@ -5236,6 +5237,7 @@ InstructionCost X86TTIImpl::getInterleavedMemoryOpCostAVX2( {6, MVT::v2i32, 9}, // interleave 6 x 2i32 into 12i32 (and store) {6, MVT::v4i32, 12}, // interleave 6 x 4i32 into 24i32 (and store) {6, MVT::v8i32, 33}, // interleave 6 x 8i32 into 48i32 (and store) + {6, MVT::v16i32, 66}, // interleave 6 x 16i32 into 96i32 (and store) }; if (Opcode == Instruction::Load) { diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-6.ll b/llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-6.ll index 674ba30..efc0175 100644 --- a/llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-6.ll +++ b/llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-6.ll @@ -27,7 +27,7 @@ target triple = "x86_64-unknown-linux-gnu" ; AVX2: LV: Found an estimated cost of 8 for VF 2 For instruction: %v0 = load float, float* %in0, align 4 ; AVX2: LV: Found an estimated cost of 18 for VF 4 For instruction: %v0 = load float, float* %in0, align 4 ; AVX2: LV: Found an estimated cost of 37 for VF 8 For instruction: %v0 = load float, float* %in0, align 4 -; AVX2: LV: Found an estimated cost of 228 for VF 16 For instruction: %v0 = load float, float* %in0, align 4 +; AVX2: LV: Found an estimated cost of 76 for VF 16 For instruction: %v0 = load float, float* %in0, align 4 ; ; AVX512: LV: Found an estimated cost of 1 for VF 1 For instruction: %v0 = load float, float* %in0, align 4 ; AVX512: LV: Found an estimated cost of 7 for VF 2 For instruction: %v0 = load float, float* %in0, align 4 diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-6.ll b/llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-6.ll index ae69382..1786cdc 100644 --- a/llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-6.ll +++ b/llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-6.ll @@ -27,7 +27,7 @@ target triple = "x86_64-unknown-linux-gnu" ; AVX2: LV: Found an estimated cost of 8 for VF 2 For instruction: %v0 = load i32, i32* %in0, align 4 ; AVX2: LV: Found an estimated cost of 18 for VF 4 For instruction: %v0 = load i32, i32* %in0, align 4 ; AVX2: LV: Found an estimated cost of 37 for VF 8 For instruction: %v0 = load i32, i32* %in0, align 4 -; AVX2: LV: Found an estimated cost of 276 for VF 16 For instruction: %v0 = load i32, i32* %in0, align 4 +; AVX2: LV: Found an estimated cost of 76 for VF 16 For instruction: %v0 = load i32, i32* %in0, align 4 ; ; AVX512: LV: Found an estimated cost of 1 for VF 1 For instruction: %v0 = load i32, i32* %in0, align 4 ; AVX512: LV: Found an estimated cost of 7 for VF 2 For instruction: %v0 = load i32, i32* %in0, align 4 diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-f32-stride-6.ll b/llvm/test/Analysis/CostModel/X86/interleaved-store-f32-stride-6.ll index cd6912b..677b930 100644 --- a/llvm/test/Analysis/CostModel/X86/interleaved-store-f32-stride-6.ll +++ b/llvm/test/Analysis/CostModel/X86/interleaved-store-f32-stride-6.ll @@ -27,7 +27,7 @@ target triple = "x86_64-unknown-linux-gnu" ; AVX2: LV: Found an estimated cost of 11 for VF 2 For instruction: store float %v5, float* %out5, align 4 ; AVX2: LV: Found an estimated cost of 15 for VF 4 For instruction: store float %v5, float* %out5, align 4 ; AVX2: LV: Found an estimated cost of 39 for VF 8 For instruction: store float %v5, float* %out5, align 4 -; AVX2: LV: Found an estimated cost of 228 for VF 16 For instruction: store float %v5, float* %out5, align 4 +; AVX2: LV: Found an estimated cost of 78 for VF 16 For instruction: store float %v5, float* %out5, align 4 ; ; AVX512: LV: Found an estimated cost of 1 for VF 1 For instruction: store float %v5, float* %out5, align 4 ; AVX512: LV: Found an estimated cost of 8 for VF 2 For instruction: store float %v5, float* %out5, align 4 diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-i32-stride-6.ll b/llvm/test/Analysis/CostModel/X86/interleaved-store-i32-stride-6.ll index 1003d34..6cc33c3 100644 --- a/llvm/test/Analysis/CostModel/X86/interleaved-store-i32-stride-6.ll +++ b/llvm/test/Analysis/CostModel/X86/interleaved-store-i32-stride-6.ll @@ -27,7 +27,7 @@ target triple = "x86_64-unknown-linux-gnu" ; AVX2: LV: Found an estimated cost of 11 for VF 2 For instruction: store i32 %v5, i32* %out5, align 4 ; AVX2: LV: Found an estimated cost of 15 for VF 4 For instruction: store i32 %v5, i32* %out5, align 4 ; AVX2: LV: Found an estimated cost of 39 for VF 8 For instruction: store i32 %v5, i32* %out5, align 4 -; AVX2: LV: Found an estimated cost of 276 for VF 16 For instruction: store i32 %v5, i32* %out5, align 4 +; AVX2: LV: Found an estimated cost of 78 for VF 16 For instruction: store i32 %v5, i32* %out5, align 4 ; ; AVX512: LV: Found an estimated cost of 1 for VF 1 For instruction: store i32 %v5, i32* %out5, align 4 ; AVX512: LV: Found an estimated cost of 8 for VF 2 For instruction: store i32 %v5, i32* %out5, align 4