From: Lucas Stach Date: Mon, 21 Nov 2016 11:29:04 +0000 (+0100) Subject: etnaviv: enable TS also on sampler resources X-Git-Tag: upstream/17.1.0~291 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=797890bbbd3b4d5415005af782244b255cb9c488;p=platform%2Fupstream%2Fmesa.git etnaviv: enable TS also on sampler resources Fixes a performance issue with imported winsys buffers as those are marked with binding sampler view. This might require a TS flush on single pipe chips that directly sample from the rendered buffer, but otherwise seems to work fine. Signed-off-by: Lucas Stach Reviewed-by: Wladimir J. van der Laan --- diff --git a/src/gallium/drivers/etnaviv/etnaviv_surface.c b/src/gallium/drivers/etnaviv/etnaviv_surface.c index db4846a..7ac2862 100644 --- a/src/gallium/drivers/etnaviv/etnaviv_surface.c +++ b/src/gallium/drivers/etnaviv/etnaviv_surface.c @@ -64,12 +64,9 @@ etna_create_surface(struct pipe_context *pctx, struct pipe_resource *prsc, * indicate the tile status module bypasses the memory * offset and MMU. */ - /* XXX for now, don't do TS for render textures as this path - * is not stable. */ if (VIV_FEATURE(ctx->screen, chipFeatures, FAST_CLEAR) && VIV_FEATURE(ctx->screen, chipMinorFeatures0, MC20) && !DBG_ENABLED(ETNA_DBG_NO_TS) && !rsc->ts_bo && - !(rsc->base.bind & (PIPE_BIND_SAMPLER_VIEW)) && (rsc->levels[level].padded_width & ETNA_RS_WIDTH_MASK) == 0 && (rsc->levels[level].padded_height & ETNA_RS_HEIGHT_MASK) == 0) { etna_screen_resource_alloc_ts(pctx->screen, rsc);