From: Krzysztof Parzyszek <kparzysz@quicinc.com>
Date: Mon, 10 Oct 2022 22:52:38 +0000 (-0700)
Subject: [Hexagon] Switch vunpackub->op->vpackeb pattern to vzb/vshuffeb
X-Git-Tag: upstream/17.0.6~30767
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=79632163db51a11467530f9060e49f3b884e7140;p=platform%2Fupstream%2Fllvm.git

[Hexagon] Switch vunpackub->op->vpackeb pattern to vzb/vshuffeb

V6_vzb and V6_vshuffeb can use any 2 resources in a packet, while
V6_vunpackub/V6_vpackeb both need a shift resource.

Also, add patterns for shifting vectors of i8.
---

diff --git a/llvm/lib/Target/Hexagon/HexagonPatternsHVX.td b/llvm/lib/Target/Hexagon/HexagonPatternsHVX.td
index 340d5a1..e8bdc9e 100644
--- a/llvm/lib/Target/Hexagon/HexagonPatternsHVX.td
+++ b/llvm/lib/Target/Hexagon/HexagonPatternsHVX.td
@@ -634,14 +634,14 @@ let Predicates = [UseHVX] in {
            (LoVec (V6_valignb HvxVR:$Vt, HvxVR:$Vs, I32:$Rt))>;
 
   def: Pat<(HexagonVASL HVI8:$Vs, I32:$Rt),
-           (V6_vpackeb (V6_vaslh (HiVec (VZxtb HvxVR:$Vs)), I32:$Rt),
-                       (V6_vaslh (LoVec (VZxtb HvxVR:$Vs)), I32:$Rt))>;
+           (V6_vshuffeb (V6_vaslh (HiVec (V6_vzb HvxVR:$Vs)), I32:$Rt),
+                        (V6_vaslh (LoVec (V6_vzb HvxVR:$Vs)), I32:$Rt))>;
   def: Pat<(HexagonVASR HVI8:$Vs, I32:$Rt),
-           (V6_vpackeb (V6_vasrh (HiVec (VSxtb HvxVR:$Vs)), I32:$Rt),
-                       (V6_vasrh (LoVec (VSxtb HvxVR:$Vs)), I32:$Rt))>;
+           (V6_vshuffeb (V6_vasrh (HiVec (V6_vsb HvxVR:$Vs)), I32:$Rt),
+                        (V6_vasrh (LoVec (V6_vsb HvxVR:$Vs)), I32:$Rt))>;
   def: Pat<(HexagonVLSR HVI8:$Vs, I32:$Rt),
-           (V6_vpackeb (V6_vlsrh (HiVec (VZxtb HvxVR:$Vs)), I32:$Rt),
-                       (V6_vlsrh (LoVec (VZxtb HvxVR:$Vs)), I32:$Rt))>;
+           (V6_vshuffeb (V6_vlsrh (HiVec (V6_vzb HvxVR:$Vs)), I32:$Rt),
+                        (V6_vlsrh (LoVec (V6_vzb HvxVR:$Vs)), I32:$Rt))>;
 
   def: Pat<(HexagonVASL HVI16:$Vs, I32:$Rt), (V6_vaslh HvxVR:$Vs, I32:$Rt)>;
   def: Pat<(HexagonVASL HVI32:$Vs, I32:$Rt), (V6_vaslw HvxVR:$Vs, I32:$Rt)>;
@@ -655,6 +655,16 @@ let Predicates = [UseHVX] in {
   def: Pat<(add HVI32:$Vx, (HexagonVASR HVI32:$Vu, I32:$Rt)),
            (V6_vasrw_acc HvxVR:$Vx, HvxVR:$Vu, I32:$Rt)>;
 
+  def: Pat<(shl HVI8:$Vs, HVI8:$Vt),
+           (V6_vshuffeb (V6_vaslhv (HiVec (V6_vzb $Vs)), (HiVec (V6_vzb $Vt))),
+                        (V6_vaslhv (LoVec (V6_vzb $Vs)), (LoVec (V6_vzb $Vt))))>;
+  def: Pat<(sra HVI8:$Vs, HVI8:$Vt),
+           (V6_vshuffeb (V6_vasrhv (HiVec (V6_vsb $Vs)), (HiVec (V6_vzb $Vt))),
+                        (V6_vasrhv (LoVec (V6_vsb $Vs)), (LoVec (V6_vzb $Vt))))>;
+  def: Pat<(srl HVI8:$Vs, HVI8:$Vt),
+           (V6_vshuffeb (V6_vlsrhv (HiVec (V6_vzb $Vs)), (HiVec (V6_vzb $Vt))),
+                        (V6_vlsrhv (LoVec (V6_vzb $Vs)), (LoVec (V6_vzb $Vt))))>;
+
   def: Pat<(shl HVI16:$Vs, HVI16:$Vt), (V6_vaslhv HvxVR:$Vs, HvxVR:$Vt)>;
   def: Pat<(shl HVI32:$Vs, HVI32:$Vt), (V6_vaslwv HvxVR:$Vs, HvxVR:$Vt)>;
   def: Pat<(sra HVI16:$Vs, HVI16:$Vt), (V6_vasrhv HvxVR:$Vs, HvxVR:$Vt)>;
@@ -676,8 +686,8 @@ let Predicates = [UseHVX] in {
   }
 
   def: Pat<(VecI8 (ctpop HVI8:$Vs)),
-           (V6_vpackeb (V6_vpopcounth (HiVec (V6_vunpackub HvxVR:$Vs))),
-                       (V6_vpopcounth (LoVec (V6_vunpackub HvxVR:$Vs))))>;
+           (V6_vshuffeb (V6_vpopcounth (HiVec (V6_vzb HvxVR:$Vs))),
+                        (V6_vpopcounth (LoVec (V6_vzb HvxVR:$Vs))))>;
   def: Pat<(VecI16 (ctpop HVI16:$Vs)), (V6_vpopcounth HvxVR:$Vs)>;
   def: Pat<(VecI32 (ctpop HVI32:$Vs)),
            (V6_vaddw (LoVec (V6_vzh (V6_vpopcounth HvxVR:$Vs))),
@@ -685,13 +695,13 @@ let Predicates = [UseHVX] in {
 
   let Predicates = [UseHVX,UseHVXV60] in
   def: Pat<(VecI8 (ctlz HVI8:$Vs)),
-           (V6_vsubb (V6_vpackeb (V6_vcl0h (HiVec (V6_vunpackub HvxVR:$Vs))),
-                                 (V6_vcl0h (LoVec (V6_vunpackub HvxVR:$Vs)))),
+           (V6_vsubb (V6_vshuffeb (V6_vcl0h (HiVec (V6_vzb HvxVR:$Vs))),
+                                  (V6_vcl0h (LoVec (V6_vzb HvxVR:$Vs)))),
                      (V60splatib (i32 0x08)))>;
   let Predicates = [UseHVX,UseHVXV62], AddedComplexity = 10 in
   def: Pat<(VecI8 (ctlz HVI8:$Vs)),
-           (V6_vsubb (V6_vpackeb (V6_vcl0h (HiVec (V6_vunpackub HvxVR:$Vs))),
-                                 (V6_vcl0h (LoVec (V6_vunpackub HvxVR:$Vs)))),
+           (V6_vsubb (V6_vshuffeb (V6_vcl0h (HiVec (V6_vzb HvxVR:$Vs))),
+                                  (V6_vcl0h (LoVec (V6_vzb HvxVR:$Vs)))),
                      (V62splatib (i32 0x08)))>;
 
   def: Pat<(VecI16 (ctlz HVI16:$Vs)), (V6_vcl0h HvxVR:$Vs)>;
diff --git a/llvm/test/CodeGen/Hexagon/autohvx/bitcount-128b.ll b/llvm/test/CodeGen/Hexagon/autohvx/bitcount-128b.ll
index 0d735f94..d4e17f9 100644
--- a/llvm/test/CodeGen/Hexagon/autohvx/bitcount-128b.ll
+++ b/llvm/test/CodeGen/Hexagon/autohvx/bitcount-128b.ll
@@ -1,10 +1,10 @@
 ; RUN: llc -march=hexagon < %s | FileCheck %s
 
 ; CHECK-LABEL: f0
-; CHECK: v[[V00:[0-9]+]]:[[V01:[0-9]+]].uh = vunpack(v0.ub)
+; CHECK: v[[V00:[0-9]+]]:[[V01:[0-9]+]].uh = vzxt(v0.ub)
 ; CHECK-DAG: v[[V02:[0-9]+]].h = vpopcount(v[[V00]].h)
 ; CHECK-DAG: v[[V03:[0-9]+]].h = vpopcount(v[[V01]].h)
-; CHECK: v0.b = vpacke(v[[V02]].h,v[[V03]].h)
+; CHECK: v0.b = vshuffe(v[[V02]].b,v[[V03]].b)
 define <128 x i8> @f0(<128 x i8> %a0) #0 {
   %t0 = call <128 x i8> @llvm.ctpop.v128i8(<128 x i8> %a0)
   ret <128 x i8> %t0
@@ -28,11 +28,11 @@ define <32 x i32> @f2(<32 x i32> %a0) #0 {
 
 ; CHECK-LABEL: f3
 ; CHECK-DAG: r[[R30:[0-9]+]] = ##134744072
-; CHECK-DAG: v[[V31:[0-9]+]]:[[V32:[0-9]+]].uh = vunpack(v0.ub)
+; CHECK-DAG: v[[V31:[0-9]+]]:[[V32:[0-9]+]].uh = vzxt(v0.ub)
 ; CHECK: v[[V33:[0-9]+]] = vsplat(r[[R30]])
 ; CHECK-DAG: v[[V34:[0-9]+]].uh = vcl0(v[[V31]].uh)
 ; CHECK-DAG: v[[V35:[0-9]+]].uh = vcl0(v[[V32]].uh)
-; CHECK: v[[V36:[0-9]+]].b = vpacke(v[[V34]].h,v[[V35]].h)
+; CHECK: v[[V36:[0-9]+]].b = vshuffe(v[[V34]].b,v[[V35]].b)
 ; CHECK: v0.b = vsub(v[[V36]].b,v[[V33]].b)
 define <128 x i8> @f3(<128 x i8> %a0) #0 {
   %t0 = call <128 x i8> @llvm.ctlz.v128i8(<128 x i8> %a0)
@@ -64,10 +64,10 @@ define <32 x i32> @f5(<32 x i32> %a0) #0 {
 ; CHECK: v[[V65:[0-9]+]].b = vsub(v0.b,v[[V63]].b)
 ; CHECK: v[[V66:[0-9]+]] = vand(v[[V61]],v[[V65]])
 ; Ctlz:
-; CHECK: v[[V67:[0-9]+]]:[[V68:[0-9]+]].uh = vunpack(v[[V66]].ub)
+; CHECK: v[[V67:[0-9]+]]:[[V68:[0-9]+]].uh = vzxt(v[[V66]].ub)
 ; CHECK: v[[V69:[0-9]+]].uh = vcl0(v[[V68]].uh)
 ; CHECK: v[[V6A:[0-9]+]].uh = vcl0(v[[V67]].uh)
-; CHECK: v[[V6B:[0-9]+]].b = vpacke(v[[V6A]].h,v[[V69]].h)
+; CHECK: v[[V6B:[0-9]+]].b = vshuffe(v[[V6A]].b,v[[V69]].b)
 ; CHECK: v[[V6C:[0-9]+]].b = vsub(v[[V6B]].b,v[[V64]].b)
 ; CHECK: v0.b = vsub(v[[V64]].b,v[[V6C]].b)
 define <128 x i8> @f6(<128 x i8> %a0) #0 {
diff --git a/llvm/test/CodeGen/Hexagon/autohvx/bitcount-64b.ll b/llvm/test/CodeGen/Hexagon/autohvx/bitcount-64b.ll
index 95cedad..586f0a3 100644
--- a/llvm/test/CodeGen/Hexagon/autohvx/bitcount-64b.ll
+++ b/llvm/test/CodeGen/Hexagon/autohvx/bitcount-64b.ll
@@ -1,10 +1,10 @@
 ; RUN: llc -march=hexagon < %s | FileCheck %s
 
 ; CHECK-LABEL: f0
-; CHECK: v[[V00:[0-9]+]]:[[V01:[0-9]+]].uh = vunpack(v0.ub)
+; CHECK: v[[V00:[0-9]+]]:[[V01:[0-9]+]].uh = vzxt(v0.ub)
 ; CHECK-DAG: v[[V02:[0-9]+]].h = vpopcount(v[[V00]].h)
 ; CHECK-DAG: v[[V03:[0-9]+]].h = vpopcount(v[[V01]].h)
-; CHECK: v0.b = vpacke(v[[V02]].h,v[[V03]].h)
+; CHECK: v0.b = vshuffe(v[[V02]].b,v[[V03]].b)
 define <64 x i8> @f0(<64 x i8> %a0) #0 {
   %t0 = call <64 x i8> @llvm.ctpop.v64i8(<64 x i8> %a0)
   ret <64 x i8> %t0
@@ -28,11 +28,11 @@ define <16 x i32> @f2(<16 x i32> %a0) #0 {
 
 ; CHECK-LABEL: f3
 ; CHECK-DAG: r[[R30:[0-9]+]] = ##134744072
-; CHECK-DAG: v[[V31:[0-9]+]]:[[V32:[0-9]+]].uh = vunpack(v0.ub)
+; CHECK-DAG: v[[V31:[0-9]+]]:[[V32:[0-9]+]].uh = vzxt(v0.ub)
 ; CHECK: v[[V33:[0-9]+]] = vsplat(r[[R30]])
 ; CHECK-DAG: v[[V34:[0-9]+]].uh = vcl0(v[[V31]].uh)
 ; CHECK-DAG: v[[V35:[0-9]+]].uh = vcl0(v[[V32]].uh)
-; CHECK: v[[V36:[0-9]+]].b = vpacke(v[[V34]].h,v[[V35]].h)
+; CHECK: v[[V36:[0-9]+]].b = vshuffe(v[[V34]].b,v[[V35]].b)
 ; CHECK: v0.b = vsub(v[[V36]].b,v[[V33]].b)
 define <64 x i8> @f3(<64 x i8> %a0) #0 {
   %t0 = call <64 x i8> @llvm.ctlz.v64i8(<64 x i8> %a0)
@@ -64,10 +64,10 @@ define <16 x i32> @f5(<16 x i32> %a0) #0 {
 ; CHECK: v[[V65:[0-9]+]].b = vsub(v0.b,v[[V63]].b)
 ; CHECK: v[[V66:[0-9]+]] = vand(v[[V61]],v[[V65]])
 ; Ctlz:
-; CHECK: v[[V67:[0-9]+]]:[[V68:[0-9]+]].uh = vunpack(v[[V66]].ub)
+; CHECK: v[[V67:[0-9]+]]:[[V68:[0-9]+]].uh = vzxt(v[[V66]].ub)
 ; CHECK: v[[V69:[0-9]+]].uh = vcl0(v[[V68]].uh)
 ; CHECK: v[[V6A:[0-9]+]].uh = vcl0(v[[V67]].uh)
-; CHECK: v[[V6B:[0-9]+]].b = vpacke(v[[V6A]].h,v[[V69]].h)
+; CHECK: v[[V6B:[0-9]+]].b = vshuffe(v[[V6A]].b,v[[V69]].b)
 ; CHECK: v[[V6C:[0-9]+]].b = vsub(v[[V6B]].b,v[[V64]].b)
 ; CHECK: v0.b = vsub(v[[V64]].b,v[[V6C]].b)
 define <64 x i8> @f6(<64 x i8> %a0) #0 {
diff --git a/llvm/test/CodeGen/Hexagon/autohvx/shift-128b.ll b/llvm/test/CodeGen/Hexagon/autohvx/shift-128b.ll
index d1eab22..d324ab2 100644
--- a/llvm/test/CodeGen/Hexagon/autohvx/shift-128b.ll
+++ b/llvm/test/CodeGen/Hexagon/autohvx/shift-128b.ll
@@ -1,62 +1,157 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -march=hexagon < %s | FileCheck %s
 
+define <128 x i8> @test0000(<128 x i8> %a0, i8 %a1) #0 {
 ; CHECK-LABEL: test0000:
-; CHECK: v0.h = vasl(v0.h,r0)
-define <64 x i16> @test0000(<64 x i16> %a0, i16 %a1) #0 {
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    {
+; CHECK-NEXT:     v1:0.uh = vzxt(v0.ub)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     v0.h = vasl(v0.h,r0)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     v1.h = vasl(v1.h,r0)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     v0.b = vshuffe(v1.b,v0.b)
+; CHECK-NEXT:     jumpr r31
+; CHECK-NEXT:    }
+  %b0 = insertelement <128 x i8> zeroinitializer, i8 %a1, i32 0
+  %b1 = shufflevector <128 x i8> %b0, <128 x i8> undef, <128 x i32> zeroinitializer
+  %v0 = shl <128 x i8> %a0, %b1
+  ret <128 x i8> %v0
+}
+
+define <128 x i8> @test0001(<128 x i8> %a0, i8 %a1) #0 {
+; CHECK-LABEL: test0001:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    {
+; CHECK-NEXT:     v1:0.h = vsxt(v0.b)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     v0.h = vasr(v0.h,r0)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     v1.h = vasr(v1.h,r0)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     v0.b = vshuffe(v1.b,v0.b)
+; CHECK-NEXT:     jumpr r31
+; CHECK-NEXT:    }
+  %b0 = insertelement <128 x i8> zeroinitializer, i8 %a1, i32 0
+  %b1 = shufflevector <128 x i8> %b0, <128 x i8> undef, <128 x i32> zeroinitializer
+  %v0 = ashr <128 x i8> %a0, %b1
+  ret <128 x i8> %v0
+}
+
+define <128 x i8> @test0002(<128 x i8> %a0, i8 %a1) #0 {
+; CHECK-LABEL: test0002:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    {
+; CHECK-NEXT:     v1:0.uh = vzxt(v0.ub)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     v0.uh = vlsr(v0.uh,r0)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     v1.uh = vlsr(v1.uh,r0)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     v0.b = vshuffe(v1.b,v0.b)
+; CHECK-NEXT:     jumpr r31
+; CHECK-NEXT:    }
+  %b0 = insertelement <128 x i8> zeroinitializer, i8 %a1, i32 0
+  %b1 = shufflevector <128 x i8> %b0, <128 x i8> undef, <128 x i32> zeroinitializer
+  %v0 = lshr <128 x i8> %a0, %b1
+  ret <128 x i8> %v0
+}
+
+define <64 x i16> @test0010(<64 x i16> %a0, i16 %a1) #0 {
+; CHECK-LABEL: test0010:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    {
+; CHECK-NEXT:     v0.h = vasl(v0.h,r0)
+; CHECK-NEXT:     jumpr r31
+; CHECK-NEXT:    }
   %b0 = insertelement <64 x i16> zeroinitializer, i16 %a1, i32 0
   %b1 = shufflevector <64 x i16> %b0, <64 x i16> undef, <64 x i32> zeroinitializer
   %v0 = shl <64 x i16> %a0, %b1
   ret <64 x i16> %v0
 }
 
-; CHECK-LABEL: test0001:
-; CHECK: v0.h = vasr(v0.h,r0)
-define <64 x i16> @test0001(<64 x i16> %a0, i16 %a1) #0 {
+define <64 x i16> @test0011(<64 x i16> %a0, i16 %a1) #0 {
+; CHECK-LABEL: test0011:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    {
+; CHECK-NEXT:     v0.h = vasr(v0.h,r0)
+; CHECK-NEXT:     jumpr r31
+; CHECK-NEXT:    }
   %b0 = insertelement <64 x i16> zeroinitializer, i16 %a1, i32 0
   %b1 = shufflevector <64 x i16> %b0, <64 x i16> undef, <64 x i32> zeroinitializer
   %v0 = ashr <64 x i16> %a0, %b1
   ret <64 x i16> %v0
 }
 
-; CHECK-LABEL: test0002:
-; CHECK: v0.uh = vlsr(v0.uh,r0)
-define <64 x i16> @test0002(<64 x i16> %a0, i16 %a1) #0 {
+define <64 x i16> @test0012(<64 x i16> %a0, i16 %a1) #0 {
+; CHECK-LABEL: test0012:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    {
+; CHECK-NEXT:     v0.uh = vlsr(v0.uh,r0)
+; CHECK-NEXT:     jumpr r31
+; CHECK-NEXT:    }
   %b0 = insertelement <64 x i16> zeroinitializer, i16 %a1, i32 0
   %b1 = shufflevector <64 x i16> %b0, <64 x i16> undef, <64 x i32> zeroinitializer
   %v0 = lshr <64 x i16> %a0, %b1
   ret <64 x i16> %v0
 }
 
-; CHECK-LABEL: test0010:
-; CHECK: v0.w = vasl(v0.w,r0)
-define <32 x i32> @test0010(<32 x i32> %a0, i32 %a1) #0 {
+define <32 x i32> @test0020(<32 x i32> %a0, i32 %a1) #0 {
+; CHECK-LABEL: test0020:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    {
+; CHECK-NEXT:     v0.w = vasl(v0.w,r0)
+; CHECK-NEXT:     jumpr r31
+; CHECK-NEXT:    }
   %b0 = insertelement <32 x i32> zeroinitializer, i32 %a1, i32 0
   %b1 = shufflevector <32 x i32> %b0, <32 x i32> undef, <32 x i32> zeroinitializer
   %v0 = shl <32 x i32> %a0, %b1
   ret <32 x i32> %v0
 }
 
-; CHECK-LABEL: test0011:
-; CHECK: v0.w = vasr(v0.w,r0)
-define <32 x i32> @test0011(<32 x i32> %a0, i32 %a1) #0 {
+define <32 x i32> @test0021(<32 x i32> %a0, i32 %a1) #0 {
+; CHECK-LABEL: test0021:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    {
+; CHECK-NEXT:     v0.w = vasr(v0.w,r0)
+; CHECK-NEXT:     jumpr r31
+; CHECK-NEXT:    }
   %b0 = insertelement <32 x i32> zeroinitializer, i32 %a1, i32 0
   %b1 = shufflevector <32 x i32> %b0, <32 x i32> undef, <32 x i32> zeroinitializer
   %v0 = ashr <32 x i32> %a0, %b1
   ret <32 x i32> %v0
 }
 
-; CHECK-LABEL: test0012:
-; CHECK: v0.uw = vlsr(v0.uw,r0)
-define <32 x i32> @test0012(<32 x i32> %a0, i32 %a1) #0 {
+define <32 x i32> @test0022(<32 x i32> %a0, i32 %a1) #0 {
+; CHECK-LABEL: test0022:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    {
+; CHECK-NEXT:     v0.uw = vlsr(v0.uw,r0)
+; CHECK-NEXT:     jumpr r31
+; CHECK-NEXT:    }
   %b0 = insertelement <32 x i32> zeroinitializer, i32 %a1, i32 0
   %b1 = shufflevector <32 x i32> %b0, <32 x i32> undef, <32 x i32> zeroinitializer
   %v0 = lshr <32 x i32> %a0, %b1
   ret <32 x i32> %v0
 }
 
-; CHECK-LABEL: test0013:
-; CHECK: v0.w += vasl(v1.w,r0)
-define <32 x i32> @test0013(<32 x i32> %a0, <32 x i32> %a1, i32 %a2) #0 {
+define <32 x i32> @test0023(<32 x i32> %a0, <32 x i32> %a1, i32 %a2) #0 {
+; CHECK-LABEL: test0023:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    {
+; CHECK-NEXT:     v0.w += vasl(v1.w,r0)
+; CHECK-NEXT:     jumpr r31
+; CHECK-NEXT:    }
   %b0 = insertelement <32 x i32> zeroinitializer, i32 %a2, i32 0
   %b1 = shufflevector <32 x i32> %b0, <32 x i32> undef, <32 x i32> zeroinitializer
   %v0 = shl <32 x i32> %a1, %b1
@@ -64,9 +159,13 @@ define <32 x i32> @test0013(<32 x i32> %a0, <32 x i32> %a1, i32 %a2) #0 {
   ret <32 x i32> %v1
 }
 
-; CHECK-LABEL: test0014:
-; CHECK: v0.w += vasr(v1.w,r0)
-define <32 x i32> @test0014(<32 x i32> %a0, <32 x i32> %a1, i32 %a2) #0 {
+define <32 x i32> @test0024(<32 x i32> %a0, <32 x i32> %a1, i32 %a2) #0 {
+; CHECK-LABEL: test0024:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    {
+; CHECK-NEXT:     v0.w += vasr(v1.w,r0)
+; CHECK-NEXT:     jumpr r31
+; CHECK-NEXT:    }
   %b0 = insertelement <32 x i32> zeroinitializer, i32 %a2, i32 0
   %b1 = shufflevector <32 x i32> %b0, <32 x i32> undef, <32 x i32> zeroinitializer
   %v0 = ashr <32 x i32> %a1, %b1
@@ -74,44 +173,131 @@ define <32 x i32> @test0014(<32 x i32> %a0, <32 x i32> %a1, i32 %a2) #0 {
   ret <32 x i32> %v1
 }
 
-; CHECK-LABEL: test0020:
-; CHECK: v0.h = vasl(v0.h,v1.h)
-define <64 x i16> @test0020(<64 x i16> %a0, <64 x i16> %a1) #0 {
+define <128 x i8> @test0030(<128 x i8> %a0, <128 x i8> %a1) #0 {
+; CHECK-LABEL: test0030:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    {
+; CHECK-NEXT:     v3:2.uh = vzxt(v0.ub)
+; CHECK-NEXT:     v31:30.uh = vzxt(v1.ub)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     v0.h = vasl(v2.h,v30.h)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     v1.h = vasl(v3.h,v31.h)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     v0.b = vshuffe(v1.b,v0.b)
+; CHECK-NEXT:     jumpr r31
+; CHECK-NEXT:    }
+  %v0 = shl <128 x i8> %a0, %a1
+  ret <128 x i8> %v0
+}
+
+define <128 x i8> @test0031(<128 x i8> %a0, <128 x i8> %a1) #0 {
+; CHECK-LABEL: test0031:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    {
+; CHECK-NEXT:     v3:2.h = vsxt(v0.b)
+; CHECK-NEXT:     v31:30.uh = vzxt(v1.ub)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     v0.h = vasr(v2.h,v30.h)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     v1.h = vasr(v3.h,v31.h)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     v0.b = vshuffe(v1.b,v0.b)
+; CHECK-NEXT:     jumpr r31
+; CHECK-NEXT:    }
+  %v0 = ashr <128 x i8> %a0, %a1
+  ret <128 x i8> %v0
+}
+
+define <128 x i8> @test0032(<128 x i8> %a0, <128 x i8> %a1) #0 {
+; CHECK-LABEL: test0032:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    {
+; CHECK-NEXT:     v3:2.uh = vzxt(v0.ub)
+; CHECK-NEXT:     v31:30.uh = vzxt(v1.ub)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     v0.h = vlsr(v2.h,v30.h)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     v1.h = vlsr(v3.h,v31.h)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     v0.b = vshuffe(v1.b,v0.b)
+; CHECK-NEXT:     jumpr r31
+; CHECK-NEXT:    }
+  %v0 = lshr <128 x i8> %a0, %a1
+  ret <128 x i8> %v0
+}
+
+define <64 x i16> @test0040(<64 x i16> %a0, <64 x i16> %a1) #0 {
+; CHECK-LABEL: test0040:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    {
+; CHECK-NEXT:     v0.h = vasl(v0.h,v1.h)
+; CHECK-NEXT:     jumpr r31
+; CHECK-NEXT:    }
   %v0 = shl <64 x i16> %a0, %a1
   ret <64 x i16> %v0
 }
 
-; CHECK-LABEL: test0021:
-; CHECK: v0.h = vasr(v0.h,v1.h)
-define <64 x i16> @test0021(<64 x i16> %a0, <64 x i16> %a1) #0 {
+define <64 x i16> @test0041(<64 x i16> %a0, <64 x i16> %a1) #0 {
+; CHECK-LABEL: test0041:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    {
+; CHECK-NEXT:     v0.h = vasr(v0.h,v1.h)
+; CHECK-NEXT:     jumpr r31
+; CHECK-NEXT:    }
   %v0 = ashr <64 x i16> %a0, %a1
   ret <64 x i16> %v0
 }
 
-; CHECK-LABEL: test0022:
-; CHECK: v0.h = vlsr(v0.h,v1.h)
-define <64 x i16> @test0022(<64 x i16> %a0, <64 x i16> %a1) #0 {
+define <64 x i16> @test0042(<64 x i16> %a0, <64 x i16> %a1) #0 {
+; CHECK-LABEL: test0042:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    {
+; CHECK-NEXT:     v0.h = vlsr(v0.h,v1.h)
+; CHECK-NEXT:     jumpr r31
+; CHECK-NEXT:    }
   %v0 = lshr <64 x i16> %a0, %a1
   ret <64 x i16> %v0
 }
 
-; CHECK-LABEL: test0030:
-; CHECK: v0.w = vasl(v0.w,v1.w)
-define <32 x i32> @test0030(<32 x i32> %a0, <32 x i32> %a1) #0 {
+define <32 x i32> @test0050(<32 x i32> %a0, <32 x i32> %a1) #0 {
+; CHECK-LABEL: test0050:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    {
+; CHECK-NEXT:     v0.w = vasl(v0.w,v1.w)
+; CHECK-NEXT:     jumpr r31
+; CHECK-NEXT:    }
   %v0 = shl <32 x i32> %a0, %a1
   ret <32 x i32> %v0
 }
 
-; CHECK-LABEL: test0031:
-; CHECK: v0.w = vasr(v0.w,v1.w)
-define <32 x i32> @test0031(<32 x i32> %a0, <32 x i32> %a1) #0 {
+define <32 x i32> @test0051(<32 x i32> %a0, <32 x i32> %a1) #0 {
+; CHECK-LABEL: test0051:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    {
+; CHECK-NEXT:     v0.w = vasr(v0.w,v1.w)
+; CHECK-NEXT:     jumpr r31
+; CHECK-NEXT:    }
   %v0 = ashr <32 x i32> %a0, %a1
   ret <32 x i32> %v0
 }
 
-; CHECK-LABEL: test0032:
-; CHECK: v0.w = vlsr(v0.w,v1.w)
-define <32 x i32> @test0032(<32 x i32> %a0, <32 x i32> %a1) #0 {
+define <32 x i32> @test0052(<32 x i32> %a0, <32 x i32> %a1) #0 {
+; CHECK-LABEL: test0052:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    {
+; CHECK-NEXT:     v0.w = vlsr(v0.w,v1.w)
+; CHECK-NEXT:     jumpr r31
+; CHECK-NEXT:    }
   %v0 = lshr <32 x i32> %a0, %a1
   ret <32 x i32> %v0
 }
diff --git a/llvm/test/CodeGen/Hexagon/autohvx/shift-64b.ll b/llvm/test/CodeGen/Hexagon/autohvx/shift-64b.ll
index 678a97c..637a342 100644
--- a/llvm/test/CodeGen/Hexagon/autohvx/shift-64b.ll
+++ b/llvm/test/CodeGen/Hexagon/autohvx/shift-64b.ll
@@ -1,8 +1,79 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -march=hexagon < %s | FileCheck %s
 
+define <64 x i8> @test0000(<64 x i8> %a0, i8 %a1) #0 {
 ; CHECK-LABEL: test0000:
-; CHECK: v0.h = vasl(v0.h,r0)
-define <32 x i16> @test0000(<32 x i16> %a0, i16 %a1) #0 {
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    {
+; CHECK-NEXT:     v1:0.uh = vzxt(v0.ub)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     v0.h = vasl(v0.h,r0)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     v1.h = vasl(v1.h,r0)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     v0.b = vshuffe(v1.b,v0.b)
+; CHECK-NEXT:     jumpr r31
+; CHECK-NEXT:    }
+  %b0 = insertelement <64 x i8> zeroinitializer, i8 %a1, i32 0
+  %b1 = shufflevector <64 x i8> %b0, <64 x i8> undef, <64 x i32> zeroinitializer
+  %v0 = shl <64 x i8> %a0, %b1
+  ret <64 x i8> %v0
+}
+
+define <64 x i8> @test0001(<64 x i8> %a0, i8 %a1) #0 {
+; CHECK-LABEL: test0001:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    {
+; CHECK-NEXT:     v1:0.h = vsxt(v0.b)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     v0.h = vasr(v0.h,r0)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     v1.h = vasr(v1.h,r0)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     v0.b = vshuffe(v1.b,v0.b)
+; CHECK-NEXT:     jumpr r31
+; CHECK-NEXT:    }
+  %b0 = insertelement <64 x i8> zeroinitializer, i8 %a1, i32 0
+  %b1 = shufflevector <64 x i8> %b0, <64 x i8> undef, <64 x i32> zeroinitializer
+  %v0 = ashr <64 x i8> %a0, %b1
+  ret <64 x i8> %v0
+}
+
+define <64 x i8> @test0002(<64 x i8> %a0, i8 %a1) #0 {
+; CHECK-LABEL: test0002:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    {
+; CHECK-NEXT:     v1:0.uh = vzxt(v0.ub)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     v0.uh = vlsr(v0.uh,r0)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     v1.uh = vlsr(v1.uh,r0)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     v0.b = vshuffe(v1.b,v0.b)
+; CHECK-NEXT:     jumpr r31
+; CHECK-NEXT:    }
+  %b0 = insertelement <64 x i8> zeroinitializer, i8 %a1, i32 0
+  %b1 = shufflevector <64 x i8> %b0, <64 x i8> undef, <64 x i32> zeroinitializer
+  %v0 = lshr <64 x i8> %a0, %b1
+  ret <64 x i8> %v0
+}
+
+define <32 x i16> @test0010(<32 x i16> %a0, i16 %a1) #0 {
+; CHECK-LABEL: test0010:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    {
+; CHECK-NEXT:     v0.h = vasl(v0.h,r0)
+; CHECK-NEXT:     jumpr r31
+; CHECK-NEXT:    }
   %b0 = insertelement <32 x i16> zeroinitializer, i16 %a1, i32 0
   %b1 = shufflevector <32 x i16> %b0, <32 x i16> undef, <32 x i32> zeroinitializer
 
@@ -10,54 +81,78 @@ define <32 x i16> @test0000(<32 x i16> %a0, i16 %a1) #0 {
   ret <32 x i16> %v0
 }
 
-; CHECK-LABEL: test0001:
-; CHECK: v0.h = vasr(v0.h,r0)
-define <32 x i16> @test0001(<32 x i16> %a0, i16 %a1) #0 {
+define <32 x i16> @test0011(<32 x i16> %a0, i16 %a1) #0 {
+; CHECK-LABEL: test0011:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    {
+; CHECK-NEXT:     v0.h = vasr(v0.h,r0)
+; CHECK-NEXT:     jumpr r31
+; CHECK-NEXT:    }
   %b0 = insertelement <32 x i16> zeroinitializer, i16 %a1, i32 0
   %b1 = shufflevector <32 x i16> %b0, <32 x i16> undef, <32 x i32> zeroinitializer
   %v0 = ashr <32 x i16> %a0, %b1
   ret <32 x i16> %v0
 }
 
-; CHECK-LABEL: test0002:
-; CHECK: v0.uh = vlsr(v0.uh,r0)
-define <32 x i16> @test0002(<32 x i16> %a0, i16 %a1) #0 {
+define <32 x i16> @test0012(<32 x i16> %a0, i16 %a1) #0 {
+; CHECK-LABEL: test0012:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    {
+; CHECK-NEXT:     v0.uh = vlsr(v0.uh,r0)
+; CHECK-NEXT:     jumpr r31
+; CHECK-NEXT:    }
   %b0 = insertelement <32 x i16> zeroinitializer, i16 %a1, i32 0
   %b1 = shufflevector <32 x i16> %b0, <32 x i16> undef, <32 x i32> zeroinitializer
   %v0 = lshr <32 x i16> %a0, %b1
   ret <32 x i16> %v0
 }
 
-; CHECK-LABEL: test0010:
-; CHECK: v0.w = vasl(v0.w,r0)
-define <16 x i32> @test0010(<16 x i32> %a0, i32 %a1) #0 {
+define <16 x i32> @test0020(<16 x i32> %a0, i32 %a1) #0 {
+; CHECK-LABEL: test0020:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    {
+; CHECK-NEXT:     v0.w = vasl(v0.w,r0)
+; CHECK-NEXT:     jumpr r31
+; CHECK-NEXT:    }
   %b0 = insertelement <16 x i32> zeroinitializer, i32 %a1, i32 0
   %b1 = shufflevector <16 x i32> %b0, <16 x i32> undef, <16 x i32> zeroinitializer
   %v0 = shl <16 x i32> %a0, %b1
   ret <16 x i32> %v0
 }
 
-; CHECK-LABEL: test0011:
-; CHECK: v0.w = vasr(v0.w,r0)
-define <16 x i32> @test0011(<16 x i32> %a0, i32 %a1) #0 {
+define <16 x i32> @test0021(<16 x i32> %a0, i32 %a1) #0 {
+; CHECK-LABEL: test0021:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    {
+; CHECK-NEXT:     v0.w = vasr(v0.w,r0)
+; CHECK-NEXT:     jumpr r31
+; CHECK-NEXT:    }
   %b0 = insertelement <16 x i32> zeroinitializer, i32 %a1, i32 0
   %b1 = shufflevector <16 x i32> %b0, <16 x i32> undef, <16 x i32> zeroinitializer
   %v0 = ashr <16 x i32> %a0, %b1
   ret <16 x i32> %v0
 }
 
-; CHECK-LABEL: test0012:
-; CHECK: v0.uw = vlsr(v0.uw,r0)
-define <16 x i32> @test0012(<16 x i32> %a0, i32 %a1) #0 {
+define <16 x i32> @test0022(<16 x i32> %a0, i32 %a1) #0 {
+; CHECK-LABEL: test0022:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    {
+; CHECK-NEXT:     v0.uw = vlsr(v0.uw,r0)
+; CHECK-NEXT:     jumpr r31
+; CHECK-NEXT:    }
   %b0 = insertelement <16 x i32> zeroinitializer, i32 %a1, i32 0
   %b1 = shufflevector <16 x i32> %b0, <16 x i32> undef, <16 x i32> zeroinitializer
   %v0 = lshr <16 x i32> %a0, %b1
   ret <16 x i32> %v0
 }
 
-; CHECK-LABEL: test0013:
-; CHECK: v0.w += vasl(v1.w,r0)
-define <16 x i32> @test0013(<16 x i32> %a0, <16 x i32> %a1, i32 %a2) #0 {
+define <16 x i32> @test0023(<16 x i32> %a0, <16 x i32> %a1, i32 %a2) #0 {
+; CHECK-LABEL: test0023:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    {
+; CHECK-NEXT:     v0.w += vasl(v1.w,r0)
+; CHECK-NEXT:     jumpr r31
+; CHECK-NEXT:    }
   %b0 = insertelement <16 x i32> zeroinitializer, i32 %a2, i32 0
   %b1 = shufflevector <16 x i32> %b0, <16 x i32> undef, <16 x i32> zeroinitializer
   %v0 = shl <16 x i32> %a1, %b1
@@ -65,9 +160,13 @@ define <16 x i32> @test0013(<16 x i32> %a0, <16 x i32> %a1, i32 %a2) #0 {
   ret <16 x i32> %v1
 }
 
-; CHECK-LABEL: test0014:
-; CHECK: v0.w += vasr(v1.w,r0)
-define <16 x i32> @test0014(<16 x i32> %a0, <16 x i32> %a1, i32 %a2) #0 {
+define <16 x i32> @test0024(<16 x i32> %a0, <16 x i32> %a1, i32 %a2) #0 {
+; CHECK-LABEL: test0024:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    {
+; CHECK-NEXT:     v0.w += vasr(v1.w,r0)
+; CHECK-NEXT:     jumpr r31
+; CHECK-NEXT:    }
   %b0 = insertelement <16 x i32> zeroinitializer, i32 %a2, i32 0
   %b1 = shufflevector <16 x i32> %b0, <16 x i32> undef, <16 x i32> zeroinitializer
   %v0 = ashr <16 x i32> %a1, %b1
@@ -75,44 +174,131 @@ define <16 x i32> @test0014(<16 x i32> %a0, <16 x i32> %a1, i32 %a2) #0 {
   ret <16 x i32> %v1
 }
 
-; CHECK-LABEL: test0020:
-; CHECK: v0.h = vasl(v0.h,v1.h)
-define <32 x i16> @test0020(<32 x i16> %a0, <32 x i16> %a1) #0 {
+define <64 x i8> @test0030(<64 x i8> %a0, <64 x i8> %a1) #0 {
+; CHECK-LABEL: test0030:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    {
+; CHECK-NEXT:     v3:2.uh = vzxt(v0.ub)
+; CHECK-NEXT:     v31:30.uh = vzxt(v1.ub)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     v0.h = vasl(v2.h,v30.h)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     v1.h = vasl(v3.h,v31.h)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     v0.b = vshuffe(v1.b,v0.b)
+; CHECK-NEXT:     jumpr r31
+; CHECK-NEXT:    }
+  %v0 = shl <64 x i8> %a0, %a1
+  ret <64 x i8> %v0
+}
+
+define <64 x i8> @test0031(<64 x i8> %a0, <64 x i8> %a1) #0 {
+; CHECK-LABEL: test0031:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    {
+; CHECK-NEXT:     v3:2.h = vsxt(v0.b)
+; CHECK-NEXT:     v31:30.uh = vzxt(v1.ub)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     v0.h = vasr(v2.h,v30.h)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     v1.h = vasr(v3.h,v31.h)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     v0.b = vshuffe(v1.b,v0.b)
+; CHECK-NEXT:     jumpr r31
+; CHECK-NEXT:    }
+  %v0 = ashr <64 x i8> %a0, %a1
+  ret <64 x i8> %v0
+}
+
+define <64 x i8> @test0032(<64 x i8> %a0, <64 x i8> %a1) #0 {
+; CHECK-LABEL: test0032:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    {
+; CHECK-NEXT:     v3:2.uh = vzxt(v0.ub)
+; CHECK-NEXT:     v31:30.uh = vzxt(v1.ub)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     v0.h = vlsr(v2.h,v30.h)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     v1.h = vlsr(v3.h,v31.h)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     v0.b = vshuffe(v1.b,v0.b)
+; CHECK-NEXT:     jumpr r31
+; CHECK-NEXT:    }
+  %v0 = lshr <64 x i8> %a0, %a1
+  ret <64 x i8> %v0
+}
+
+define <32 x i16> @test0040(<32 x i16> %a0, <32 x i16> %a1) #0 {
+; CHECK-LABEL: test0040:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    {
+; CHECK-NEXT:     v0.h = vasl(v0.h,v1.h)
+; CHECK-NEXT:     jumpr r31
+; CHECK-NEXT:    }
   %v0 = shl <32 x i16> %a0, %a1
   ret <32 x i16> %v0
 }
 
-; CHECK-LABEL: test0021:
-; CHECK: v0.h = vasr(v0.h,v1.h)
-define <32 x i16> @test0021(<32 x i16> %a0, <32 x i16> %a1) #0 {
+define <32 x i16> @test0041(<32 x i16> %a0, <32 x i16> %a1) #0 {
+; CHECK-LABEL: test0041:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    {
+; CHECK-NEXT:     v0.h = vasr(v0.h,v1.h)
+; CHECK-NEXT:     jumpr r31
+; CHECK-NEXT:    }
   %v0 = ashr <32 x i16> %a0, %a1
   ret <32 x i16> %v0
 }
 
-; CHECK-LABEL: test0022:
-; CHECK: v0.h = vlsr(v0.h,v1.h)
-define <32 x i16> @test0022(<32 x i16> %a0, <32 x i16> %a1) #0 {
+define <32 x i16> @test0042(<32 x i16> %a0, <32 x i16> %a1) #0 {
+; CHECK-LABEL: test0042:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    {
+; CHECK-NEXT:     v0.h = vlsr(v0.h,v1.h)
+; CHECK-NEXT:     jumpr r31
+; CHECK-NEXT:    }
   %v0 = lshr <32 x i16> %a0, %a1
   ret <32 x i16> %v0
 }
 
-; CHECK-LABEL: test0030:
-; CHECK: v0.w = vasl(v0.w,v1.w)
-define <16 x i32> @test0030(<16 x i32> %a0, <16 x i32> %a1) #0 {
+define <16 x i32> @test0050(<16 x i32> %a0, <16 x i32> %a1) #0 {
+; CHECK-LABEL: test0050:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    {
+; CHECK-NEXT:     v0.w = vasl(v0.w,v1.w)
+; CHECK-NEXT:     jumpr r31
+; CHECK-NEXT:    }
   %v0 = shl <16 x i32> %a0, %a1
   ret <16 x i32> %v0
 }
 
-; CHECK-LABEL: test0031:
-; CHECK: v0.w = vasr(v0.w,v1.w)
-define <16 x i32> @test0031(<16 x i32> %a0, <16 x i32> %a1) #0 {
+define <16 x i32> @test0051(<16 x i32> %a0, <16 x i32> %a1) #0 {
+; CHECK-LABEL: test0051:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    {
+; CHECK-NEXT:     v0.w = vasr(v0.w,v1.w)
+; CHECK-NEXT:     jumpr r31
+; CHECK-NEXT:    }
   %v0 = ashr <16 x i32> %a0, %a1
   ret <16 x i32> %v0
 }
 
-; CHECK-LABEL: test0032:
-; CHECK: v0.w = vlsr(v0.w,v1.w)
-define <16 x i32> @test0032(<16 x i32> %a0, <16 x i32> %a1) #0 {
+define <16 x i32> @test0052(<16 x i32> %a0, <16 x i32> %a1) #0 {
+; CHECK-LABEL: test0052:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    {
+; CHECK-NEXT:     v0.w = vlsr(v0.w,v1.w)
+; CHECK-NEXT:     jumpr r31
+; CHECK-NEXT:    }
   %v0 = lshr <16 x i32> %a0, %a1
   ret <16 x i32> %v0
 }