From: Kazu Hirata <kazu@google.com>
Date: Sun, 12 Mar 2023 19:00:14 +0000 (-0700)
Subject: [InstCombine] Precommit tests
X-Git-Tag: upstream/17.0.6~15111
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=7946e67cf3e30271d60c08490fd6cd93bd771fe8;p=platform%2Fupstream%2Fllvm.git

[InstCombine] Precommit tests

This patch precommits tests for:

https://github.com/llvm/llvm-project/issues/60802
https://github.com/llvm/llvm-project/issues/61183

which are about std::bit_ceil and std::bit_floor, respectively.
---

diff --git a/llvm/test/Transforms/InstCombine/bit_ceil.ll b/llvm/test/Transforms/InstCombine/bit_ceil.ll
new file mode 100644
index 0000000..440ab3d
--- /dev/null
+++ b/llvm/test/Transforms/InstCombine/bit_ceil.ll
@@ -0,0 +1,43 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -passes=instcombine -S | FileCheck %s
+
+define i32 @bit_ceil_32(i32 %x) {
+; CHECK-LABEL: @bit_ceil_32(
+; CHECK-NEXT:    [[DEC:%.*]] = add i32 [[X:%.*]], -1
+; CHECK-NEXT:    [[CTLZ:%.*]] = tail call i32 @llvm.ctlz.i32(i32 [[DEC]], i1 false), !range [[RNG0:![0-9]+]]
+; CHECK-NEXT:    [[SUB:%.*]] = sub nuw nsw i32 32, [[CTLZ]]
+; CHECK-NEXT:    [[SHL:%.*]] = shl nuw i32 1, [[SUB]]
+; CHECK-NEXT:    [[UGT:%.*]] = icmp ugt i32 [[X]], 1
+; CHECK-NEXT:    [[SEL:%.*]] = select i1 [[UGT]], i32 [[SHL]], i32 1
+; CHECK-NEXT:    ret i32 [[SEL]]
+;
+  %dec = add i32 %x, -1
+  %ctlz = tail call i32 @llvm.ctlz.i32(i32 %dec, i1 false)
+  %sub = sub i32 32, %ctlz
+  %shl = shl i32 1, %sub
+  %ugt = icmp ugt i32 %x, 1
+  %sel = select i1 %ugt, i32 %shl, i32 1
+  ret i32 %sel
+}
+
+define i64 @bit_ceil_64(i64 %x) {
+; CHECK-LABEL: @bit_ceil_64(
+; CHECK-NEXT:    [[DEC:%.*]] = add i64 [[X:%.*]], -1
+; CHECK-NEXT:    [[CTLZ:%.*]] = tail call i64 @llvm.ctlz.i64(i64 [[DEC]], i1 false), !range [[RNG1:![0-9]+]]
+; CHECK-NEXT:    [[SUB:%.*]] = sub nuw nsw i64 64, [[CTLZ]]
+; CHECK-NEXT:    [[SHL:%.*]] = shl nuw i64 1, [[SUB]]
+; CHECK-NEXT:    [[UGT:%.*]] = icmp ugt i64 [[X]], 1
+; CHECK-NEXT:    [[SEL:%.*]] = select i1 [[UGT]], i64 [[SHL]], i64 1
+; CHECK-NEXT:    ret i64 [[SEL]]
+;
+  %dec = add i64 %x, -1
+  %ctlz = tail call i64 @llvm.ctlz.i64(i64 %dec, i1 false)
+  %sub = sub i64 64, %ctlz
+  %shl = shl i64 1, %sub
+  %ugt = icmp ugt i64 %x, 1
+  %sel = select i1 %ugt, i64 %shl, i64 1
+  ret i64 %sel
+}
+
+declare i32 @llvm.ctlz.i32(i32, i1 immarg)
+declare i64 @llvm.ctlz.i64(i64, i1 immarg)
diff --git a/llvm/test/Transforms/InstCombine/bit_floor.ll b/llvm/test/Transforms/InstCombine/bit_floor.ll
new file mode 100644
index 0000000..0ef7fe3
--- /dev/null
+++ b/llvm/test/Transforms/InstCombine/bit_floor.ll
@@ -0,0 +1,43 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -passes=instcombine -S | FileCheck %s
+
+define i32 @bit_floor_32(i32 %x) {
+; CHECK-LABEL: @bit_floor_32(
+; CHECK-NEXT:    [[EQ0:%.*]] = icmp eq i32 [[X:%.*]], 0
+; CHECK-NEXT:    [[LSHR:%.*]] = lshr i32 [[X]], 1
+; CHECK-NEXT:    [[CTLZ:%.*]] = tail call i32 @llvm.ctlz.i32(i32 [[LSHR]], i1 false), !range [[RNG0:![0-9]+]]
+; CHECK-NEXT:    [[SUB:%.*]] = sub nuw nsw i32 32, [[CTLZ]]
+; CHECK-NEXT:    [[SHL:%.*]] = shl nuw i32 1, [[SUB]]
+; CHECK-NEXT:    [[SEL:%.*]] = select i1 [[EQ0]], i32 0, i32 [[SHL]]
+; CHECK-NEXT:    ret i32 [[SEL]]
+;
+  %eq0 = icmp eq i32 %x, 0
+  %lshr = lshr i32 %x, 1
+  %ctlz = tail call i32 @llvm.ctlz.i32(i32 %lshr, i1 false)
+  %sub = sub i32 32, %ctlz
+  %shl = shl i32 1, %sub
+  %sel = select i1 %eq0, i32 0, i32 %shl
+  ret i32 %sel
+}
+
+define i64 @bit_floor_64(i64 %x) {
+; CHECK-LABEL: @bit_floor_64(
+; CHECK-NEXT:    [[EQ0:%.*]] = icmp eq i64 [[X:%.*]], 0
+; CHECK-NEXT:    [[LSHR:%.*]] = lshr i64 [[X]], 1
+; CHECK-NEXT:    [[CTLZ:%.*]] = tail call i64 @llvm.ctlz.i64(i64 [[LSHR]], i1 false), !range [[RNG1:![0-9]+]]
+; CHECK-NEXT:    [[SUB:%.*]] = sub nuw nsw i64 64, [[CTLZ]]
+; CHECK-NEXT:    [[SHL:%.*]] = shl nuw i64 1, [[SUB]]
+; CHECK-NEXT:    [[SEL:%.*]] = select i1 [[EQ0]], i64 0, i64 [[SHL]]
+; CHECK-NEXT:    ret i64 [[SEL]]
+;
+  %eq0 = icmp eq i64 %x, 0
+  %lshr = lshr i64 %x, 1
+  %ctlz = tail call i64 @llvm.ctlz.i64(i64 %lshr, i1 false)
+  %sub = sub i64 64, %ctlz
+  %shl = shl i64 1, %sub
+  %sel = select i1 %eq0, i64 0, i64 %shl
+  ret i64 %sel
+}
+
+declare i32 @llvm.ctlz.i32(i32, i1 immarg)
+declare i64 @llvm.ctlz.i64(i64, i1 immarg)