From: Caesar Wang <wxt@rock-chips.com>
Date: Wed, 27 Jul 2016 14:24:06 +0000 (+0800)
Subject: arm64: dts: rockchip: add reset saradc node for rk3368 SoCs
X-Git-Tag: v5.15~12933^2^2~1
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=78ec79bfd59e126e1cb394302bfa531a420b3ecd;p=platform%2Fkernel%2Flinux-starfive.git

arm64: dts: rockchip: add reset saradc node for rk3368 SoCs

SARADC controller needs to be reset before programming it, otherwise
it will not function properly.

Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Cc: <Stable@vger.kernel.org>
Signed-off-by: Jonathan Cameron <jic23@kernel.org>
---

diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
index d02a9003..4f44d11 100644
--- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
@@ -270,6 +270,8 @@
 		#io-channel-cells = <1>;
 		clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 		clock-names = "saradc", "apb_pclk";
+		resets = <&cru SRST_SARADC>;
+		reset-names = "saradc-apb";
 		status = "disabled";
 	};