From: Mark Zhang Date: Tue, 16 Oct 2012 08:31:49 +0000 (+0800) Subject: ARM: tegra30: clk: Fix output_rate overflow X-Git-Tag: v3.7-rc2~4^2~5^2~2 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=786621308cfbb9421a54773e57dbdbe504c417cc;p=profile%2Fcommon%2Fkernel-common.git ARM: tegra30: clk: Fix output_rate overflow Change the type of variable from "unsigned long" to "u64". This avoids the overflow while clock rate calculating. Signed-off-by: Mark Zhang Signed-off-by: Stephen Warren --- diff --git a/arch/arm/mach-tegra/tegra30_clocks.c b/arch/arm/mach-tegra/tegra30_clocks.c index 5cd502c..e9de5df 100644 --- a/arch/arm/mach-tegra/tegra30_clocks.c +++ b/arch/arm/mach-tegra/tegra30_clocks.c @@ -1199,7 +1199,7 @@ static long tegra30_pll_round_rate(struct clk_hw *hw, unsigned long rate, { struct clk_tegra *c = to_clk_tegra(hw); unsigned long input_rate = *prate; - unsigned long output_rate = *prate; + u64 output_rate = *prate; const struct clk_pll_freq_table *sel; struct clk_pll_freq_table cfg; int mul;