From: Marek Olšák Date: Tue, 17 Sep 2019 02:31:48 +0000 (-0400) Subject: radeonsi: initialize displayable DCC using the retile blit to prevent hangs X-Git-Tag: upstream/19.3.0~1672 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=783fae2a1fcb61c92717921108cad7ef78daa36a;p=platform%2Fupstream%2Fmesa.git radeonsi: initialize displayable DCC using the retile blit to prevent hangs Cc 19.2 --- diff --git a/src/gallium/drivers/radeonsi/si_texture.c b/src/gallium/drivers/radeonsi/si_texture.c index 5f4fd60..a8504f4 100644 --- a/src/gallium/drivers/radeonsi/si_texture.c +++ b/src/gallium/drivers/radeonsi/si_texture.c @@ -1448,9 +1448,17 @@ si_texture_create_object(struct pipe_screen *screen, } } - /* Upload the DCC retile map. */ + /* Initialize displayable DCC that requires the retile blit. */ if (tex->surface.dcc_retile_map_offset) { - /* Use a staging buffer for the upload, because + /* Uninitialized DCC can hang the display hw. + * Clear to white to indicate that. */ + si_screen_clear_buffer(sscreen, &tex->buffer.b.b, + tex->surface.display_dcc_offset, + tex->surface.u.gfx9.display_dcc_size, + DCC_CLEAR_COLOR_1111); + + /* Upload the DCC retile map. + * Use a staging buffer for the upload, because * the buffer backing the texture is unmappable. */ bool use_uint16 = tex->surface.u.gfx9.dcc_retile_use_uint16;