From: Leonid Yegoshin Date: Mon, 24 Nov 2014 15:42:46 +0000 (+0000) Subject: MIPS: mm: tlbex: Use cpu_has_mips_r2_exec_hazard for the EHB instruction X-Git-Tag: v4.0-rc1~4^2~26^2~23 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=77f3ee59ee7cfe19e0ee48d9a990c7967fbfcbed;p=platform%2Fkernel%2Flinux-exynos.git MIPS: mm: tlbex: Use cpu_has_mips_r2_exec_hazard for the EHB instruction MIPS uses the cpu_has_mips_r2_exec_hazard macro to determine whether the EHB instruction is available or not. This is necessary for MIPS R6 which also supports the EHB instruction. Signed-off-by: Leonid Yegoshin Signed-off-by: Markos Chandras --- diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index ff8d99c..d75ff73 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -501,7 +501,7 @@ static void build_tlb_write_entry(u32 **p, struct uasm_label **l, case tlb_indexed: tlbw = uasm_i_tlbwi; break; } - if (cpu_has_mips_r2) { + if (cpu_has_mips_r2_exec_hazard) { /* * The architecture spec says an ehb is required here, * but a number of cores do not have the hazard and @@ -1953,7 +1953,7 @@ static void build_r4000_tlb_load_handler(void) switch (current_cpu_type()) { default: - if (cpu_has_mips_r2) { + if (cpu_has_mips_r2_exec_hazard) { uasm_i_ehb(&p); case CPU_CAVIUM_OCTEON: @@ -2020,7 +2020,7 @@ static void build_r4000_tlb_load_handler(void) switch (current_cpu_type()) { default: - if (cpu_has_mips_r2) { + if (cpu_has_mips_r2_exec_hazard) { uasm_i_ehb(&p); case CPU_CAVIUM_OCTEON: