From: Palmer Dabbelt Date: Thu, 21 Apr 2022 17:03:55 +0000 (-0700) Subject: RISC-V: Only default to spinwait on SBI-0.1 and M-mode X-Git-Tag: v6.1-rc5~1154^2~9 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=77d707a310fa908d796d00e6c26b650cf2b4442f;p=platform%2Fkernel%2Flinux-starfive.git RISC-V: Only default to spinwait on SBI-0.1 and M-mode The spinwait boot method has been superseded by the SBI HSM extension for some time now, but it still enabled by default. This causes some issues on large hart count systems, which will hang if a physical hart exists that is larger than NR_CPUS. Users on modern SBI implementation don't need spinwait, and while it's probably possible to deal with some of the spinwait issues let's just restrict the default to systems that are likely to actually use it. Signed-off-by: Palmer Dabbelt Reviewed-by: Atish Patra Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20220421170354.10555-1-palmer@rivosinc.com Signed-off-by: Palmer Dabbelt --- diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 905e550..c22f581 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -396,7 +396,7 @@ config RISCV_SBI_V01 config RISCV_BOOT_SPINWAIT bool "Spinwait booting method" depends on SMP - default y + default y if RISCV_SBI_V01 || RISCV_M_MODE help This enables support for booting Linux via spinwait method. In the spinwait method, all cores randomly jump to Linux. One of the cores @@ -407,6 +407,12 @@ config RISCV_BOOT_SPINWAIT rely on ordered booting via SBI HSM extension which gets chosen dynamically at runtime if the firmware supports it. + Since spinwait is incompatible with sparse hart IDs, it requires + NR_CPUS be large enough to contain the physical hart ID of the first + hart to enter Linux. + + If unsure what to do here, say N. + config KEXEC bool "Kexec system call" select KEXEC_CORE