From: Chris Forbes Date: Thu, 8 May 2014 04:29:41 +0000 (+1200) Subject: i965/Gen7: Set up layer constraints properly for depth buffers X-Git-Tag: upstream/10.3~2127 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=77d55ef4819436ebbf9786a1e720ec00707bbb19;p=platform%2Fupstream%2Fmesa.git i965/Gen7: Set up layer constraints properly for depth buffers Again, a few problems: - Layered attachments did not honor MinLayer. - Non-layered MSAA attachments rendered to the wrong layer due to dividing by the layer count. All depth buffers use the IMS layout, so the physical layer count == logical layer count. - Layered attachments were not limited to irb->layer_count, so we could render off the end of the texture. V2: Restore the MAX2() to account for zero depth/layer_count. Signed-off-by: Chris Forbes Reviewed-by: Kenneth Graunke --- diff --git a/src/mesa/drivers/dri/i965/gen7_misc_state.c b/src/mesa/drivers/dri/i965/gen7_misc_state.c index b6759f1..d8efa76 100644 --- a/src/mesa/drivers/dri/i965/gen7_misc_state.c +++ b/src/mesa/drivers/dri/i965/gen7_misc_state.c @@ -65,7 +65,7 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw, rb = (struct gl_renderbuffer*) irb; if (rb) { - depth = MAX2(rb->Depth, 1); + depth = MAX2(irb->layer_count, 1); if (rb->TexImage) gl_target = rb->TexImage->TexObject->Target; } @@ -81,19 +81,16 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw, surftype = BRW_SURFACE_2D; depth *= 6; break; + case GL_TEXTURE_3D: + assert(rb); + depth = MAX2(rb->Depth, 1); + /* fallthrough */ default: surftype = translate_tex_target(gl_target); break; } - if (fb->MaxNumLayers > 0 || !irb) { - min_array_element = 0; - } else if (irb->mt->num_samples > 1) { - /* Convert physical layer to logical layer. */ - min_array_element = irb->mt_layer / irb->mt->num_samples; - } else { - min_array_element = irb->mt_layer; - } + min_array_element = irb ? irb->mt_layer : 0; lod = irb ? irb->mt_level - irb->mt->first_level : 0;