From: Vasily Khoruzhick Date: Tue, 7 Mar 2023 21:26:46 +0000 (-0800) Subject: rockchip: sdhci: rk3568: fix clock setting logic X-Git-Tag: v2023.07~81^2~57 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=7786710adb76720be8e693c4efcea039af7ae086;p=platform%2Fkernel%2Fu-boot.git rockchip: sdhci: rk3568: fix clock setting logic mmc->tran_speed is max clock, but currently rk3568_sdhci_set_ios_post uses it if its != 0, regardless of mmc->clock value, and it breaks eMMC controller. Without this patch 'mmc dev 0; mmc dev 1; mmc dev 0' is enough for breaking eMMC, since first initialization sets mmc->mmc_tran speed to non-zero value (26MHz in my case), and on subsequent re-init when mmc layer asks for 400KHz it sets 26MHz instead. Fix it by using MAX(mmc->tran_speed, mmc->clock) Signed-off-by: Vasily Khoruzhick Reviewed-by: Kever Yang --- diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c index e1409dd..fef23f5 100644 --- a/drivers/mmc/rockchip_sdhci.c +++ b/drivers/mmc/rockchip_sdhci.c @@ -401,11 +401,11 @@ static int rk3568_sdhci_set_enhanced_strobe(struct sdhci_host *host) static int rk3568_sdhci_set_ios_post(struct sdhci_host *host) { struct mmc *mmc = host->mmc; - uint clock = mmc->tran_speed; + uint clock = mmc->clock; u32 reg, vendor_reg; - if (!clock) - clock = mmc->clock; + if (mmc->tran_speed && mmc->clock > mmc->tran_speed) + clock = mmc->tran_speed; rk3568_sdhci_emmc_set_clock(host, clock);