From: Paul Burton Date: Tue, 22 Sep 2015 17:26:37 +0000 (-0700) Subject: MIPS: Clarify mips_cm_is64 documentation X-Git-Tag: v4.4-rc1~6^2~102 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=7784494ae7864a112d4858b2b494e0358ec412a1;p=platform%2Fkernel%2Flinux-exynos.git MIPS: Clarify mips_cm_is64 documentation The documentation for mips_cm_is64 implied that the width of the CM GCRs would change depending upon the CPU, which is not true. Reword the explanation to be clearer that the GCR width is purely dependent upon the version of the CM. Signed-off-by: Paul Burton Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: James Hogan Cc: Markos Chandras Patchwork: https://patchwork.linux-mips.org/patch/11185/ Signed-off-by: Ralf Baechle --- diff --git a/arch/mips/include/asm/mips-cm.h b/arch/mips/include/asm/mips-cm.h index d66d0e0..465a7c1 100644 --- a/arch/mips/include/asm/mips-cm.h +++ b/arch/mips/include/asm/mips-cm.h @@ -36,12 +36,12 @@ extern phys_addr_t __mips_cm_phys_base(void); /* * mips_cm_is64 - determine CM register width * - * The CM register width is processor and CM specific. A 64-bit processor - * usually has a 64-bit CM and a 32-bit one has a 32-bit CM but a 64-bit - * processor could come with a 32-bit CM. Moreover, accesses on 64-bit CMs - * can be done either using regular 64-bit load/store instructions, or 32-bit - * load/store instruction on 32-bit register pairs. We opt for using 64-bit - * accesses on 64-bit CMs and kernels and 32-bit in any other case. + * The CM register width is determined by the version of the CM, with CM3 + * introducing 64 bit GCRs and all prior CM versions having 32 bit GCRs. + * However we may run a kernel built for MIPS32 on a system with 64 bit GCRs, + * or vice-versa. This variable indicates the width of the memory accesses + * that the kernel will perform to GCRs, which may differ from the actual + * width of the GCRs. * * It's set to 0 for 32-bit accesses and 1 for 64-bit accesses. */