From: Aswath Govindraju <a-govindraju@ti.com>
Date: Wed, 16 Jun 2021 16:38:21 +0000 (+0530)
Subject: arm: dts: k3-am64-main: Reserve OCMRAM for DMSC-lite and secure proxy communication
X-Git-Tag: v2021.10~95^2~25
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=776e25788c744fe91f7e720331a17ad0ff050480;p=platform%2Fkernel%2Fu-boot.git

arm: dts: k3-am64-main: Reserve OCMRAM for DMSC-lite and secure proxy communication

The final 128KB in SRAM is reserved by default for DMSC-lite code and
secure proxy communication buffer. The memory region used for DMSC-lite
code can be optionally freed up by secure firmware API[1]. However, the
buffer for secure proxy communication is not configurable. This default
hardware configuration is unique for AM64.

Therefore, indicate the area reserved for DMSC-lite code and secure proxy
communication buffer in the oc_sram device tree node.

[1] - http://downloads.ti.com/tisci/esd/latest/6_topic_user_guides/security_handover.html#triggering-security-handover

Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Acked-by: Suman Anna <s-anna@ti.com>
Link: https://lore.kernel.org/r/20210616163821.20457-3-a-govindraju@ti.com
---

diff --git a/arch/arm/dts/k3-am64-main.dtsi b/arch/arm/dts/k3-am64-main.dtsi
index f68b969..c5af2ff 100644
--- a/arch/arm/dts/k3-am64-main.dtsi
+++ b/arch/arm/dts/k3-am64-main.dtsi
@@ -16,6 +16,14 @@
 		tfa-sram@1c0000 {
 			reg = <0x1c0000 0x20000>;
 		};
+
+		dmsc-sram@1e0000 {
+			reg = <0x1e0000 0x1c000>;
+		};
+
+		sproxy-sram@1fc000 {
+			reg = <0x1fc000 0x4000>;
+		};
 	};
 
 	gic500: interrupt-controller@1800000 {