From: Ilia Mirkin <imirkin@alum.mit.edu>
Date: Thu, 23 Jul 2015 06:27:04 +0000 (-0400)
Subject: nvc0/ir: add hazard for 2nd dim of vfetch/load indirect argument
X-Git-Tag: upstream/17.1.0~17466
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=77672cdb64e9c19e974fe5985050709fc317498e;p=platform%2Fupstream%2Fmesa.git

nvc0/ir: add hazard for 2nd dim of vfetch/load indirect argument

Apparently a multi-word load can potentially overwrite the indirect
sources, so make sure that RA picks different registers for those.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
---

diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp
index 898653c..78bc97f 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp
@@ -2066,6 +2066,8 @@ RegAlloc::InsertConstraintsPass::visit(BasicBlock *bb)
          condenseDefs(i);
          if (i->src(0).isIndirect(0) && typeSizeof(i->dType) >= 8)
             addHazard(i, i->src(0).getIndirect(0));
+         if (i->src(0).isIndirect(1) && typeSizeof(i->dType) >= 8)
+            addHazard(i, i->src(0).getIndirect(1));
       } else
       if (i->op == OP_UNION ||
           i->op == OP_MERGE ||