From: Krzysztof Parzyszek Date: Mon, 14 May 2018 20:09:07 +0000 (+0000) Subject: [Hexagon] Add a target feature for memop generation X-Git-Tag: llvmorg-7.0.0-rc1~6065 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=771f2422d06b1aca660333ff89ef62529e395f27;p=platform%2Fupstream%2Fllvm.git [Hexagon] Add a target feature for memop generation llvm-svn: 332285 --- diff --git a/llvm/lib/Target/Hexagon/Hexagon.td b/llvm/lib/Target/Hexagon/Hexagon.td index bd36077..265f80f 100644 --- a/llvm/lib/Target/Hexagon/Hexagon.td +++ b/llvm/lib/Target/Hexagon/Hexagon.td @@ -48,6 +48,8 @@ def FeatureLongCalls: SubtargetFeature<"long-calls", "UseLongCalls", "true", "Use constant-extended calls">; def FeatureMemNoShuf: SubtargetFeature<"mem_noshuf", "HasMemNoShuf", "false", "Supports mem_noshuf feature">; +def FeatureMemops: SubtargetFeature<"memops", "UseMemops", "true", + "Use memop instructions">; def FeatureNVJ: SubtargetFeature<"nvj", "UseNewValueJumps", "true", "Support for new-value jumps", [FeaturePackets]>; def FeatureDuplex: SubtargetFeature<"duplex", "EnableDuplex", "true", @@ -59,7 +61,7 @@ def FeatureReservedR19: SubtargetFeature<"reserved-r19", "ReservedR19", // Hexagon Instruction Predicate Definitions. //===----------------------------------------------------------------------===// -def UseMEMOP : Predicate<"HST->useMemOps()">; +def UseMEMOPS : Predicate<"HST->useMemops()">; def IEEERndNearV5T : Predicate<"HST->modeIEEERndNear()">; def UseHVX64B : Predicate<"HST->useHVX64BOps()">, AssemblerPredicate<"ExtensionHVX64B">; @@ -318,21 +320,24 @@ class Proc; def : Proc<"hexagonv4", HexagonModelV4, - [ArchV4, FeaturePackets, FeatureNVJ, FeatureDuplex]>; + [ArchV4, + FeatureDuplex, FeatureMemops, FeatureNVJ, FeaturePackets]>; def : Proc<"hexagonv5", HexagonModelV4, - [ArchV4, ArchV5, FeaturePackets, FeatureNVJ, FeatureDuplex]>; + [ArchV4, ArchV5, + FeatureDuplex, FeatureMemops, FeatureNVJ, FeaturePackets]>; def : Proc<"hexagonv55", HexagonModelV55, - [ArchV4, ArchV5, ArchV55, FeaturePackets, FeatureNVJ, - FeatureDuplex]>; + [ArchV4, ArchV5, ArchV55, + FeatureDuplex, FeatureMemops, FeatureNVJ, FeaturePackets]>; def : Proc<"hexagonv60", HexagonModelV60, - [ArchV4, ArchV5, ArchV55, ArchV60, FeaturePackets, FeatureNVJ, - FeatureDuplex]>; + [ArchV4, ArchV5, ArchV55, ArchV60, + FeatureDuplex, FeatureMemops, FeatureNVJ, FeaturePackets]>; def : Proc<"hexagonv62", HexagonModelV62, - [ArchV4, ArchV5, ArchV55, ArchV60, ArchV62, FeaturePackets, - FeatureNVJ, FeatureDuplex]>; + [ArchV4, ArchV5, ArchV55, ArchV60, ArchV62, + FeatureDuplex, FeatureMemops, FeatureNVJ, FeaturePackets]>; def : Proc<"hexagonv65", HexagonModelV65, [ArchV4, ArchV5, ArchV55, ArchV60, ArchV62, ArchV65, - FeatureMemNoShuf, FeaturePackets, FeatureNVJ, FeatureDuplex]>; + FeatureDuplex, FeatureMemNoShuf, FeatureMemops, FeatureNVJ, + FeaturePackets]>; //===----------------------------------------------------------------------===// // Declare the target which we are implementing diff --git a/llvm/lib/Target/Hexagon/HexagonPatterns.td b/llvm/lib/Target/Hexagon/HexagonPatterns.td index 3615633..781c285 100644 --- a/llvm/lib/Target/Hexagon/HexagonPatterns.td +++ b/llvm/lib/Target/Hexagon/HexagonPatterns.td @@ -2581,8 +2581,10 @@ multiclass Memopxr_add_pat { - defm: Memopxr_base_pat ; - defm: Memopxr_add_pat ; + let Predicates = [UseMEMOPS] in { + defm: Memopxr_base_pat ; + defm: Memopxr_add_pat ; + } } let AddedComplexity = 200 in { @@ -2680,8 +2682,10 @@ multiclass Memopxi_add_pat { - defm: Memopxi_base_pat ; - defm: Memopxi_add_pat ; + let Predicates = [UseMEMOPS] in { + defm: Memopxi_base_pat ; + defm: Memopxi_add_pat ; + } } let AddedComplexity = 220 in { diff --git a/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp b/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp index 781d388..743fe39 100644 --- a/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp +++ b/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp @@ -39,13 +39,6 @@ using namespace llvm; #define GET_SUBTARGETINFO_TARGET_DESC #include "HexagonGenSubtargetInfo.inc" -static cl::opt EnableMemOps("enable-hexagon-memops", - cl::Hidden, cl::ZeroOrMore, cl::ValueDisallowed, cl::init(true), - cl::desc("Generate V4 MEMOP in code generation for Hexagon target")); - -static cl::opt DisableMemOps("disable-hexagon-memops", - cl::Hidden, cl::ZeroOrMore, cl::ValueDisallowed, cl::init(false), - cl::desc("Do not generate V4 MEMOP in code generation for Hexagon target")); static cl::opt EnableIEEERndNear("enable-hexagon-ieee-rnd-near", cl::Hidden, cl::ZeroOrMore, cl::init(false), @@ -61,9 +54,6 @@ static cl::opt EnableDotCurSched("enable-cur-sched", cl::Hidden, cl::ZeroOrMore, cl::init(true), cl::desc("Enable the scheduler to generate .cur")); -static cl::opt EnableVecFrwdSched("enable-evec-frwd-sched", - cl::Hidden, cl::ZeroOrMore, cl::init(true)); - static cl::opt DisableHexagonMISched("disable-hexagon-misched", cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::desc("Disable Hexagon MI Scheduling")); @@ -124,7 +114,6 @@ HexagonSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) { UseHVX64BOps = false; UseLongCalls = false; - UseMemOps = DisableMemOps ? false : EnableMemOps; ModeIEEERndNear = EnableIEEERndNear; UseBSBScheduling = hasV60TOps() && EnableBSBSched; diff --git a/llvm/lib/Target/Hexagon/HexagonSubtarget.h b/llvm/lib/Target/Hexagon/HexagonSubtarget.h index fd564f2..f6111b7 100644 --- a/llvm/lib/Target/Hexagon/HexagonSubtarget.h +++ b/llvm/lib/Target/Hexagon/HexagonSubtarget.h @@ -46,11 +46,14 @@ class Triple; class HexagonSubtarget : public HexagonGenSubtargetInfo { virtual void anchor(); - bool UseMemOps, UseHVX64BOps, UseHVX128BOps; - bool UseLongCalls; + bool UseHVX64BOps = false; + bool UseHVX128BOps = false; + bool ModeIEEERndNear = false; + + bool UseLongCalls = false; + bool UseMemops = false; bool UsePackets = false; bool UseNewValueJumps = false; - bool ModeIEEERndNear; bool HasMemNoShuf = false; bool EnableDuplex = false; @@ -119,7 +122,6 @@ public: /// subtarget options. Definition of function is auto generated by tblgen. void ParseSubtargetFeatures(StringRef CPU, StringRef FS); - bool useMemOps() const { return UseMemOps; } bool hasV5TOps() const { return getHexagonArchVersion() >= Hexagon::ArchEnum::V5; } @@ -150,13 +152,14 @@ public: bool hasV65TOpsOnly() const { return getHexagonArchVersion() == Hexagon::ArchEnum::V65; } + bool useMemops() const { return UseMemops; } + bool usePackets() const { return UsePackets; } + bool useNewValueJumps() const { return UseNewValueJumps; } bool modeIEEERndNear() const { return ModeIEEERndNear; } bool useHVXOps() const { return HexagonHVXVersion > Hexagon::ArchEnum::V4; } bool useHVX128BOps() const { return useHVXOps() && UseHVX128BOps; } bool useHVX64BOps() const { return useHVXOps() && UseHVX64BOps; } - bool usePackets() const { return UsePackets; } - bool useNewValueJumps() const { return UseNewValueJumps; } bool hasMemNoShuf() const { return HasMemNoShuf; } bool hasReservedR19() const { return ReservedR19; } diff --git a/llvm/test/CodeGen/Hexagon/feature-memops.ll b/llvm/test/CodeGen/Hexagon/feature-memops.ll new file mode 100644 index 0000000..2d5103d --- /dev/null +++ b/llvm/test/CodeGen/Hexagon/feature-memops.ll @@ -0,0 +1,23 @@ +; RUN: llc -march=hexagon < %s | FileCheck %s + +; CHECK-LABEL: enabled: +; CHECK: memw({{.*}}) += #1 +define void @enabled(i32* %p) #0 { + %v0 = load i32, i32* %p + %v1 = add i32 %v0, 1 + store i32 %v1, i32* %p + ret void +} + +; CHECK-LABEL: disabled: +; CHECK-NOT: memw({{.*}}) += #1 +define void @disabled(i32* %p) #1 { + %v0 = load i32, i32* %p + %v1 = add i32 %v0, 1 + store i32 %v1, i32* %p + ret void +} + +attributes #0 = { nounwind } +attributes #1 = { nounwind "target-features"="-memops" } +