From: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Date: Mon, 22 Aug 2022 13:00:50 +0000 (+0200)
Subject: radv: remove redundant assignment of tcs.tcs_vertices_out
X-Git-Tag: upstream/22.3.5~4327
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=76f33cbf25b01ff0a13a36e85a5c7df48d4adc98;p=platform%2Fupstream%2Fmesa.git

radv: remove redundant assignment of tcs.tcs_vertices_out

It's already assigned from radv_nir_shader_info_pass() and it's only
used to configure the VGT_TF_PARAM register. Otherwise, we read it
from NIR shader info during compilation.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18184>
---

diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 40ec9cb..750866b 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -3614,7 +3614,6 @@ gather_tess_info(struct radv_device *device, struct radv_pipeline_stage *stages,
    stages[MESA_SHADER_TESS_EVAL].info.num_tess_patches = num_patches;
    stages[MESA_SHADER_GEOMETRY].info.num_tess_patches = num_patches;
    stages[MESA_SHADER_VERTEX].info.num_tess_patches = num_patches;
-   stages[MESA_SHADER_TESS_CTRL].info.tcs.tcs_vertices_out = tess_out_patch_size;
    stages[MESA_SHADER_VERTEX].info.tcs.tcs_vertices_out = tess_out_patch_size;
 
    if (!radv_use_llvm_for_stage(device, MESA_SHADER_VERTEX)) {