From: Inki Dae <inki.dae@samsung.com>
Date: Fri, 23 Nov 2018 08:30:37 +0000 (+0900)
Subject: arm: dts: exynos5422: change BPLL clock to 933MHz
X-Git-Tag: submit/tizen/20190329.020226~196
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=76ddac6c701df33a3a8e0c8f988761557ef1e162;p=platform%2Fkernel%2Flinux-exynos.git

arm: dts: exynos5422: change BPLL clock to 933MHz

This patch changes BPLL clock to 933MHz for DREX controller
can use maximum speed.

Change-Id: Ia06079c32ad532cb8a53d9dcae6a7fbacf80895a
Signed-off-by: Inki Dae <inki.dae@samsung.com>
---

diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
index 652274eaf7b3..824d608c9dad 100644
--- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
+++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
@@ -122,6 +122,11 @@
 	status = "okay";
 };
 
+&clock {
+	assigned-clocks = <&clock CLK_FOUT_BPLL>;
+	assigned-clock-rates = <933000000>;
+};
+
 &cpu0 {
 	cpu-supply = <&buck6_reg>;
 };