From: Trevor David Black Date: Fri, 3 Mar 2023 07:06:29 +0000 (+0000) Subject: Add RISC-V 64 bit support X-Git-Tag: upstream/1.3.5~2^2^2^2~2^2~1 X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=764b2f056e47178bef81c63c358aee8922a13901;p=platform%2Fupstream%2FVK-GL-CTS.git Add RISC-V 64 bit support Android is adding RISC-V support to AOSP, but only for 64-bit RISC-V. (We've only added the 32-bit constants for completeness, should others want them.) Signed-off-by: Mao Han Components: Framework, Vulkan, AOSP Google bug: 262585507 Change-Id: Ib818315bb3aa0fe6ebcf82fac846be9a60198e04 --- diff --git a/external/vulkancts/modules/vulkan/vktInfoTests.cpp b/external/vulkancts/modules/vulkan/vktInfoTests.cpp index 63052c9..bdfeab8 100644 --- a/external/vulkancts/modules/vulkan/vktInfoTests.cpp +++ b/external/vulkancts/modules/vulkan/vktInfoTests.cpp @@ -84,6 +84,8 @@ std::string getCpuName (int cpu) case DE_CPU_ARM_64: return "DE_CPU_ARM_64"; case DE_CPU_MIPS: return "DE_CPU_MIPS"; case DE_CPU_MIPS_64: return "DE_CPU_MIPS_64"; + case DE_CPU_RISCV_32: return "DE_CPU_RISCV_32"; + case DE_CPU_RISCV_64: return "DE_CPU_RISCV_64"; default: return de::toString(cpu); } diff --git a/framework/delibs/debase/deDefs.c b/framework/delibs/debase/deDefs.c index 203ce0c..078c71a 100644 --- a/framework/delibs/debase/deDefs.c +++ b/framework/delibs/debase/deDefs.c @@ -38,8 +38,8 @@ DE_STATIC_ASSERT(sizeof(deIntptr) == sizeof(void*)); DE_STATIC_ASSERT(DE_PTR_SIZE == sizeof(void*)); /* Sanity checks for DE_PTR_SIZE & DE_CPU */ -#if !((DE_CPU == DE_CPU_X86_64 || DE_CPU == DE_CPU_ARM_64 || DE_CPU == DE_CPU_MIPS_64) && (DE_PTR_SIZE == 8)) && \ - !((DE_CPU == DE_CPU_X86 || DE_CPU == DE_CPU_ARM || DE_CPU == DE_CPU_MIPS) && (DE_PTR_SIZE == 4)) +#if !((DE_CPU == DE_CPU_X86_64 || DE_CPU == DE_CPU_ARM_64 || DE_CPU == DE_CPU_MIPS_64 || DE_CPU == DE_CPU_RISCV_64) && (DE_PTR_SIZE == 8)) && \ + !((DE_CPU == DE_CPU_X86 || DE_CPU == DE_CPU_ARM || DE_CPU == DE_CPU_MIPS || DE_CPU == DE_CPU_RISCV_32) && (DE_PTR_SIZE == 4)) # error "DE_CPU and DE_PTR_SIZE mismatch" #endif diff --git a/framework/delibs/debase/deDefs.h b/framework/delibs/debase/deDefs.h index fa19567..80b240a 100644 --- a/framework/delibs/debase/deDefs.h +++ b/framework/delibs/debase/deDefs.h @@ -108,6 +108,8 @@ #define DE_CPU_ARM_64 4 #define DE_CPU_MIPS 5 #define DE_CPU_MIPS_64 6 +#define DE_CPU_RISCV_32 7 +#define DE_CPU_RISCV_64 8 /* CPU detection. */ #if defined(DE_CPU) @@ -124,6 +126,10 @@ # define DE_CPU DE_CPU_MIPS #elif defined(__mips__) && ((__mips) == 64) # define DE_CPU DE_CPU_MIPS_64 +#elif defined(__riscv) && ((__riscv_xlen) == 32) +# define DE_CPU DE_CPU_RISCV_32 +#elif defined(__riscv) && ((__riscv_xlen) == 64) +# define DE_CPU DE_CPU_RISCV_64 #else # error Unknown CPU. #endif diff --git a/modules/internal/ditBuildInfoTests.cpp b/modules/internal/ditBuildInfoTests.cpp index 056da8e..345e6ec 100644 --- a/modules/internal/ditBuildInfoTests.cpp +++ b/modules/internal/ditBuildInfoTests.cpp @@ -71,6 +71,8 @@ static const char* getCpuName (int cpu) case DE_CPU_ARM_64: return "DE_CPU_ARM_64"; case DE_CPU_MIPS: return "DE_CPU_MIPS"; case DE_CPU_MIPS_64: return "DE_CPU_MIPS_64"; + case DE_CPU_RISCV_32: return "DE_CPU_RISCV_32"; + case DE_CPU_RISCV_64: return "DE_CPU_RISCV_64"; default: return DE_NULL; }