From: Linus Torvalds <torvalds@linux-foundation.org>
Date: Thu, 2 Sep 2021 21:17:24 +0000 (-0700)
Subject: Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
X-Git-Tag: accepted/tizen/unified/20230118.172025~6482
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=75d6e7d9ced83e937757e278c3ce1ccd6606a96a;p=platform%2Fkernel%2Flinux-rpi.git

Merge tag 'clk-for-linus' of git://git./linux/kernel/git/clk/linux

Pull clk updates from Stephen Boyd:
 "Nothing changed in the clk framework core this time around. We did get
  some updates to the basic clk types to use determine_rate for the
  divider type and add a power of two fractional divider flag though.

  Otherwise, this is a collection of clk driver updates. More than half
  the diffstat is in the Qualcomm clk driver where we add a bunch of
  data to describe clks on various SoCs and fix bugs. The other big new
  thing in here is the Mediatek MT8192 clk driver. That's been under
  review for a while and it's nice to see that it's finally upstream.

  Beyond that it's the usual set of minor fixes and tweaks to clk
  drivers. There are some non-clk driver bits in here which have all
  been acked by the respective maintainers.

  New Drivers:
   - Support video, gpu, display clks on qcom sc7280 SoCs
   - GCC clks on qcom MSM8953, SM4250/6115, and SM6350 SoCs
   - Multimedia clks (MMCC) on qcom MSM8994/MSM8992
   - RPMh clks on qcom SM6350 SoCs
   - Support for Mediatek MT8192 SoCs
   - Add display (DU and DSI) clocks on Renesas R-Car V3U
   - Add I2C, DMAC, USB, sound (SSIF-2), GPIO, CANFD, and ADC clocks and
     resets on Renesas RZ/G2L

  Updates:
   - Support the SD/OE pin on IDT VersaClock 5 and 6 clock generators
   - Add power of two flag to fractional divider clk type
   - Migrate some clk drivers to clk_divider_ops.determine_rate
   - Migrate to clk_parent_data in gcc-sdm660
   - Fix CLKOUT clocks on i.MX8MM and i.MX8MN by using imx_clk_hw_mux2
   - Switch from .round_rate to .determine_rate in clk-divider-gate
   - Fix clock tree update for TF-A controlled clocks for all i.MX8M
   - Add missing M7 core clock for i.MX8MN
   - YAML conversion of rk3399 clock controller binding
   - Removal of GRF dependency for the rk3328/rk3036 pll types
   - Drop CLK_IS_CRITICAL flag from Tegra fuse clk
   - Make CLK_R9A06G032 Kconfig symbol invisible
   - Convert various DT bindings to YAML"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (128 commits)
  dt-bindings: clock: samsung: fix header path in example
  clk: tegra: fix old-style declaration
  clk: qcom: Add SM6350 GCC driver
  MAINTAINERS: clock: include S3C and S5P in Samsung SoC clock entry
  dt-bindings: clock: samsung: convert S5Pv210 AudSS to dtschema
  dt-bindings: clock: samsung: convert Exynos AudSS to dtschema
  dt-bindings: clock: samsung: convert Exynos4 to dtschema
  dt-bindings: clock: samsung: convert Exynos3250 to dtschema
  dt-bindings: clock: samsung: convert Exynos542x to dtschema
  dt-bindings: clock: samsung: add bindings for Exynos external clock
  dt-bindings: clock: samsung: convert Exynos5250 to dtschema
  clk: vc5: Add properties for configuring SD/OE behavior
  clk: vc5: Use dev_err_probe
  dt-bindings: clk: vc5: Add properties for configuring the SD/OE pin
  dt-bindings: clock: brcm,iproc-clocks: fix armpll properties
  clk: zynqmp: Fix kernel-doc format
  clk: at91: clk-generated: Limit the requested rate to our range
  clk: ralink: avoid to set 'CLK_IS_CRITICAL' flag for gates
  clk: zynqmp: Fix a memory leak
  clk: zynqmp: Check the return type
  ...
---

75d6e7d9ced83e937757e278c3ce1ccd6606a96a
diff --cc Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
index 2d4ff0c,0000000..f9ffa5b
mode 100644,000000..100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
@@@ -1,58 -1,0 +1,59 @@@
 +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
 +%YAML 1.2
 +---
 +$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mmsys.yaml#"
 +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
 +
 +title: MediaTek mmsys controller
 +
 +maintainers:
 +  - Matthias Brugger <matthias.bgg@gmail.com>
 +
 +description:
 +  The MediaTek mmsys system controller provides clock control, routing control,
 +  and miscellaneous control in mmsys partition.
 +
 +properties:
 +  $nodename:
 +    pattern: "^syscon@[0-9a-f]+$"
 +
 +  compatible:
 +    oneOf:
 +      - items:
 +          - enum:
 +              - mediatek,mt2701-mmsys
 +              - mediatek,mt2712-mmsys
 +              - mediatek,mt6765-mmsys
 +              - mediatek,mt6779-mmsys
 +              - mediatek,mt6797-mmsys
 +              - mediatek,mt8167-mmsys
 +              - mediatek,mt8173-mmsys
 +              - mediatek,mt8183-mmsys
++              - mediatek,mt8192-mmsys
 +              - mediatek,mt8365-mmsys
 +          - const: syscon
 +      - items:
 +          - const: mediatek,mt7623-mmsys
 +          - const: mediatek,mt2701-mmsys
 +          - const: syscon
 +
 +  reg:
 +    maxItems: 1
 +
 +  "#clock-cells":
 +    const: 1
 +
 +required:
 +  - compatible
 +  - reg
 +  - "#clock-cells"
 +
 +additionalProperties: false
 +
 +examples:
 +  - |
 +    mmsys: syscon@14000000 {
 +        compatible = "mediatek,mt8173-mmsys", "syscon";
 +        reg = <0x14000000 0x1000>;
 +        #clock-cells = <1>;
 +    };