From: Ulrich Weigand <ulrich.weigand@de.ibm.com>
Date: Mon, 31 Oct 2016 18:59:52 +0000 (+0000)
Subject: Fix per-processor model scheduler definition completeness check
X-Git-Tag: llvmorg-4.0.0-rc1~5821
X-Git-Url: http://review.tizen.org/git/?a=commitdiff_plain;h=75cda2f2b50f7872e129f700663251711a3a2923;p=platform%2Fupstream%2Fllvm.git

Fix per-processor model scheduler definition completeness check

The CodeGenSchedModels::checkCompleteness routine in TableGen/
CodeGenSchedule.cpp is supposed to verify for each processor
model that is marked as "complete" that it actually defines a
scheduling class for each instruction.

However, this did not work correctly due to an incorrect
check whether a scheduling class has an itinerary.

Reviewer: atrick
Differential revision: https://reviews.llvm.org/D26156

llvm-svn: 285622
---

diff --git a/llvm/utils/TableGen/CodeGenSchedule.cpp b/llvm/utils/TableGen/CodeGenSchedule.cpp
index eb7899e..4cc600d 100644
--- a/llvm/utils/TableGen/CodeGenSchedule.cpp
+++ b/llvm/utils/TableGen/CodeGenSchedule.cpp
@@ -1567,7 +1567,8 @@ void CodeGenSchedModels::checkCompleteness() {
       const CodeGenSchedClass &SC = getSchedClass(SCIdx);
       if (!SC.Writes.empty())
         continue;
-      if (SC.ItinClassDef != nullptr)
+      if (SC.ItinClassDef != nullptr &&
+          SC.ItinClassDef->getName() != "NoItinerary")
         continue;
 
       const RecVec &InstRWs = SC.InstRWs;